This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (1. 5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 µW, it has a sufficient input range, whereas conventional Wang's OTA needs 703 µW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.

This paper proposes a new method for estimating route outage probability in non-regenerative repeater digital microwave radio systems. In this method, the route outage probability is estimated by various means, including path correlation of fading occurrence and C/N degradation corresponding to the number of non-regenerative repeater stations with and without demodulator devices. In the conventional method, the path correlation is treated as 0 and the C/N degradation is taken as a constant value on each path. To confirm the proposed method's effectiveness, a field test is carried out in which 16QAM signals pass through two non-regenerative repeater stations. The results obtained are in good agreement with the estimated outage probability.

In this paper, a threshold voltage (VT) cancellation circuit for neuron-MOS (νMOS) analog circuits is described. By connecting the output terminal of this circuit with one of the input terminals of the νMOS transistor, cancellation ofVT is realized. The circuit has advantages of ground-referenced output and is insensitive to the fluctuation of bias and supply voltages. Second-order effects, such as the channel length modulation effect, the mobility reduction effect and device mismatch of the proposed circuit are analyzed in detail. Low-power and high-swing νMOS cascode current mirror is presented as an application. Performance of the proposed circuits is confirmed by HSPICE simulation with MOSIS 2. 0 µ p-well double-poly and double-metal CMOS device parameters.

Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.

The proposed high-power-factor converter is constructed with a flyback converter, and locates the energy-storage capacitor on the secondary side of the transformer. A high power-factor can be obtained without needing to detect any current, and the ZVS operation can be achieved without auxiliary switches. To make the best use of these advantages in the converter, ZVS operations and power-factor characteristics in the converter were analyzed. From the analytical results, the effective control method for achieving ZVS was examined. Using a bread-board circuit controlled by this method, a power-factor of 0.99 and a conversion efficiency of 88% were measured.

Microcellular radio direct-sequence code division multiple access (DC-CDMA) system using optical link to connect their base stations to a central station is a solution of cost-effective and efficient spectrum reuse to meet the growing demand for mobile communications. In addition to the inherent multiuser interference (MUI) of CDMA signals, the system capacity is significantly reduced by a nonlinear distortion (NLD) due to the nonlinearity of optical link. In this paper, a two-stage cancellation technique is introduced into the system to cancel both the MUI and the NLD. It is performed at the receiver of the central station where the random ingredients of all user signals are estimated, and the MUI and the NLD are rebuilt and removed from the received signal. The validity of the cancellation technique is theoretically analyzed and shown by the numerical results. The analytical method and its results are also applicable to other general nonlinear CDMA.

A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.

The cell structure of surface discharge ACPDPs with a long gap between the sustaining electrodes achieves high luminous efficiency. However, the long gap cell structure causes high firing voltage and thus makes driving more difficult than with the conventional gap cell structure. The rise in firing voltage in the long gap cell structure could not be explained by Paschen's scaling law. We derived a new governing equation for firing voltage, involving the influence of a non-uniform electric field, to investigate this deviation from Paschen's law. From the calculated results we found that changing the gap length corresponds to the change in the degree of distortion of the electric field between the sustaining electrodes.

Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2µm fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a nonuniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.

A small-sized three-stage GaAs power module has been developed for portable digital radios using M-16QAM modulation. This module has exhibited typical P1dB of 10 W with PAE of 48% and a power gain of 35 dB at a low supply voltage of 6.5 V in 1.453-1.477 GHz band. The volume of the module is only 1.5 cc, which is one of the smallest value in 10 W class modules ever reported. In order to realize the reduced size and the high power performances simultaneously, the module has employed new power divider/combiner circuits with significant features of the reduced occupation area, the improved isolation properties and the function of second-harmonic control.

A buried gate AlGaAs/InGaAs heterojunction FET (HJFET) with gate breakdown voltage of 30 V was examined for high drain bias (higher than 10 V) operation. High breakdown voltage was realized due to the optimization of the narrow recess depth. A 1.4 mm HJFET has exhibited an output power of 30.2 dBm (1050 mW) with 50% power added efficiency (PAE) and 12.1 dB linear gain at 12 GHz with a 13 V drain bias. An internal matching circuit for a 16.8 mm HJFET was designed using a large-signal load impedance determined from load-pull measurement. The 16.8 mm internally-matched HJFET has delivered 38.9 dBm (7.8 W) output power with 46% PAE and 11.6 dB linear gain at 12 GHz with a drain bias of 13 V. This is the first report of higher than 10 V operation of an X- and Ku-band power HJFET with the excellent power performance.

A high performance, high-swing CMOS cascode current mirror operating with 1V power supply voltage and using standard CMOS technology is presented. The present circuit employs PMOS source-coupled pair as voltage level shifter to reduce the power supply voltage requirement. The additional advantages of the use of the source-coupled pair are the improved output resistance and the automatic adaptive biasing, thereby enabling the high-swing of output terminal, when used in the cascode configuration. An analytical discussion of the circuit is carried out and the results are confirmed by SPICE simulation. SPICE simulation results show that the input voltage requirement is 370mV and the minimum output voltage requirement is 273mV at the maximum input current of 40µA, whose requirements decrease with decreasing input currens. The output resistance is shown to be greater than 4MΩ at the maximum output current of 40µA, which increases with decreasing output currents. The -3dB bandwidth is shown to be greater than 400MHz and the total harmonic distortion better than -54.34dB at 100kHz at the maximum peak-to-peak input current swing of 40µA. The present circuit will be useful for the low voltage, low power, high-performance mixed analog/digital signal processing.

Outage probability evaluation for a new category of wireless access systems is discussed. Wireless access systems dealt with in this paper are links which connect a portable terminal to a base station through a line-of-sight path. It is also assumed that the terminal equipment is operated in a still atate during actual communications. This mobility restriction enables the wireless access to have a capacity as high as the Mbit-order with high quality performance. Multipath fading observed in such a system may have more moderate variations than Rayleigh distribution. This paper tentatively designates the above wireless access as relocatable systems, and attempts to analyze their error performance, approximating the fading characteristics with Gamma-distribution. Also dynamic relations between bit error rate (BER) and signal-to-noise ratio are calculated under Gamma-distribution fading. Based on the analyses prediction methods for outage probability of typical QPSK systems are given, and thus it is established to design the performance aspect of relocatable systems with different features from both fixed and mobile systems.

Multipath interconnection networks can support higher bandwidth than those of nonblocking networks by passing multiple packets to the same output simultaneously and these packets are buffered in the output buffer. The delay-throughput performance of the output buffer in multipath networks is closely related to output traffic distribution, packet arrival process at each output link connected to a given output buffer. The output traffic distributions are different according to the various input traffic patterns. Focusing on nonuniform output traffic distributions, this paper develops a new, general analytic model of the output buffer in multipath networks, which enables us to investigate the delay-throughput performance of the output buffer under various input traffic patterns. This paper also introduces Multipath Crossbar network as a representative multipath network which is the base architecture of our analysis. It is shown that the output buffer performances such as packet loss probability and delay improve as nonuniformity of the output traffic distribution becomes larger.

This paper presents Super-CMOS SRAM process technology that integrates bipolar and CMOS transistors in a chip while adding only one ion implantation step and no lithography mask steps to the conventional CMOS SRAM process. The Super-CMOS SRAM process therefore has the same process cost as the CMOS SRAMs, while it achieves higher access speeds. In order to demonstrate the Super-CMOS SRAM, we have developed a 3.3 V/5 V 256 kb SRAM using 0.4 µm Super-CMOS process technology. By applying bipolar transistors to the sense amplifier circuits, a high-speed access time of 5.8 ns with a 3.0 V power supply is successfully achieved.

An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.

In a fully depleted (FD) CMOS/SIMOX device, the threshold voltage can be reduced by 0.1 V while keeping the same off current as that of bulk CMOS. This enhances gate speed at low supply voltage so that lowering supply voltage reduces both active and static power consumption without additional circuits. An LSI architecture featuring a low supply voltage for internal gates and an LVTTL interface is proposed. However, to implement the architecture with FD-CMOS/SIMOX devices, there were problems which were low drain-breakdown voltage and half electrostatic discharge (ESD) hardness compared with that of bulk CMOS devices. An LVTTL-compatible output buffer circuit is developed to overcome the low drain-breakdown voltage. Cascade circuits are applied at an output stage and a voltage converter with cross-coupled PMOS is used for reducing the applied voltage from 3.3 V to 2.2 V or less. Using this output buffer together with an LVTTL-compatible input buffer, external 3.3 V signal can be converted from/to 2.0-1.2 V signal with little static current. The cascade circuit, however, weakens the already low ESD hardness of the CMOS/SIMOX circuit. The new ESD protection circuit provides robust LVTTL compatible I/O circuits. It features lateral diodes working as drain-well-diodes in bulk CMOS and protection devices for dual power supplies. A diode/MOS merged layout pattern is used for both to dissipate heat and save area. The CMOS/SIMOX ESD protection circuit is the first one to meet the MIL standard. Using 120 kgate test LSIs made on 300 kgate array with 0.25-µm CMOS/SIMOX, 0.25-µm bulk CMOS and 0.5-µm bulk CMOS, power consumptions are compared. The 0.25-µm CMOS/SIMOX LSI can operate at an internal voltage of 1.2 V at the same frequency as the 0.5-µm LSI operating at 3.3 V. The internal supply voltage reduction scheme reduces LSI power consumption to 3% of that of 0.5-µm bulk LVTTL-LSI.