We have developed a 6-bit flash ADC powered from a single 1.8 V supply, using a bipolar based BiCMOS process. Measurements revealed that it operates up to 340 Msps at 1.26 V power supply consuming 36 mW. The conversion rate per power performance index of 9.4 Msps/mW is the highest in the fast 6-bit ADCs reported to date. To operate at this low supply voltage, a new encoder scheme, together with the unique layout, was devised which also substantially improved sparkle error rate. The encoder circuits was synthesized in a new logic topology that we named "folding logic. " This new logic topology is not only suitable for low-voltage operation but also intrinsically fast.

This paper describes low-power and low-voltage analog circuit techniques applicable to deep sub-micron LSIs in baseband and RF signal processing. The trends indicate that reductions in the supply voltage are inevitable, that power dissipation will not become sufficiently low, and that performance will improve continuously. Some circuit techniques currently being used to achieve these goals are reviewed. Next, three trial approaches are introduced. The first of these is a 1 V operational video-speed CMOS sample-and-hold IC. The second is a 1 V operational high-frequency CMOS VCO circuit. Finally, a step-down DC-DC converter IC with a 1 V output and a greater than 80% power efficiency is introduced. These approaches prove that the low-power and low-voltage operation of analog circuits can be realized without sacrificing performance.

A low-voltage silicon-on-insulator (SOI) voltage-reference circuit has been developed. It is based on threshold-voltage-summation architecture and the output is not affected by the input offset of the feedback amplifier. Thus, the output dispersion is considerably reduced. An undoped MOSFET is used as a depletion-mode transistor because of its small threshold voltage. The temperature dependence of normal and undoped MOSFETs in fully depleted CMOS/SOI technology is studied for designing a temperature-insensitive voltage-reference circuit. A prototype circuit, fabricated on a fully depleted CMOS/SIMOX process, has a measured reference voltage of 530 16.8 mV (3σ), and can operate at a supply voltage as low as 0.6 V. The measured temperature coefficient is 0.02 0.06 mV/ (3σ).

MOSFETs can be used as capacitors, but its capacitance can vary by 5 to 7 times as its terminal voltage varies. To reduce the voltage dependence of the capacitance, this paper proposed two types of devices: one is called accumulation MOSFET (AMOS) and the other is formed by two conventional PMOS connected in anti-parallel. These two devices are readily available in the standard digital CMOS processes. The proposed capacitors were implemented in three different CMOS processes. The measured results show that the capacitances of both devices have less voltage dependence than a single PMOS. The voltage dependence of the AMOS capacitance can be as small as 17%. The minimum capacitance per unit area of the AMOS is 1.8 times that of the double-poly capacitor in an analog/mixed-mode CMOS process. To verify the usefulness of these two types of capacitors, they are used as compensation capacitors in a conventional two-stage amplifier. The measured results show that the amplifier compensated by the AMOS capacitor has little variation (6%) of the unity-gain frequency over the input common-mode range. Due to its smaller die area and cheaper digital process, AMOS can be used as compensation capacitor without resorting to more expensive analog process.

The conventional average model for a pulse width modulator employed in a voltage-mode-controlled pulse width modulated converter tends to be numerically unstable when the on-time duty ratio becomes sufficiently small. This paper presents a new average model for a voltage-mode control modulator that is not susceptible to such numerical problems. The validity of the proposed model is confirmed with cycle-by-cycle simulations using an exact discrete-time model.

The surface film of a slip ring is important for the sliding contact phenomenon. The surface film is affected by atmospheric temperature, humidity and air pressure. The main objective of our study is to examine the effect of oxygen gas on the sliding contact phenomenon. In the present experiment, we examined the contact voltage drop for continuous sliding when the atmosphere is changed from low pressure to atmospheric pressure by introducing oxygen (O2 20%+N2 80%) or nitrogen gas. As a result, the contact voltage drop increases rapidly with increasing gas pressure, and its fluctuation also becomes large. These phenomena are observed in both cases of oxygen (O2 20%+N2 80%) and nitrogen introduction. The results clearly show that the sudden increase of contact voltage drop is affected by factors other than the oxide film. Actually, the oxide film is not formed in the nitrogen atmosphere. Furthermore, the frictional coefficient of carbon and copper ring is changed at ambient atmosphere. It is inferred from these data that the contact voltage drop may be affected by the frictional coefficient. When the gas pressure decreases again, the contact voltage drop does not suffer from the effect of ambient gas. Therefore, only the resistance of the oxide film appears to affect contact voltage drop. In this paper, the effect of sliding contact phenomenon on the contact voltage drop by gas adsorption and film generation was examined.

For wireless communication, a low-voltage monolithic LC-tank CMOS voltage-controlled-oscillator (VCO) is developed with 0.2-µm fully-depleted silicon-on-insulator (SOI) CMOS process technology. The VCO features a double-tuning technique to achieve a wide tuning range with lateral p-n junction varactors. The VCO has the following features at the supply voltage of 1.5 V: (1) Output frequency range from 1.07 GHz to 1.36 GHz, (2) Third-harmonic below -37 dBc, and (3) Phase noise of -120 dBc/Hz at 1 MHz offset frequency.

With the progress of integration of circuits and PCBs (Printed Circuit Boards), novel techniques have been required for verification of signal integrity. Noise analysis of the power/ground planes is one of the most important issues. This paper describes a high-speed simulator for PCBs which contain the interconnects with nonlinear terminations. This simulator is based on the environmental tool ASSIST (Assistant System for Simulation Study) constructed for development of the circuit simulators, and is combined with PRIMA (Passive Reduced-Order Interconnect Macromodeling Algorithm). In this simulator, an efficient implementation of PRIMA is considered with using a voltage-controlled current source (VCCS) model. Finally, this simulator is applied to the analysis of power/ground planes of the simple PCBs, and the validity is verified.

Self-ordered mesoporous silicate films from organic-inorganic compound materials are successfully fabricated into the surface photo voltage (SPV) type gas sensor device as a gas adsorption insulator layer. These kinds of gas sensors device exhibit NO gas sensing property dependent on their mesoporous film structure. We are succeeded in indication about a possibility of mesoporous silicate film for the SPV type gas sensor application.

This paper proposes design of new linear bipolar OTAs using hyperbolic circuits with an intermediate voltage terminal. Four types of the OTAs are presented; two OTAs contain a hyperbolic sine circuit and the other two OTAs employ a hyperbolic cosine circuit. The linear input voltage range of the proposed OTAs is wider than that of the well-known conventional OTA, multi-TANH doublet, while each proposed OTA has advantages, such as low power dissipation, high-frequency characteristics and so on. The results of SPICE simulation show that satisfactory characteristics are obtained.

In this paper, a time-to-digital converter in which the digital output is obtained without delay time is proposed. The circuit consists of a time-to-voltage converter, voltage-to-frequency converter, and counter. In the time-to-voltage converter, a capacitor is charged with a constant current during the input time interval. The change in the capacitor voltage is proportional to the input time and the capacitor voltage can be converted into a pulse signal with the voltage-to-frequency converter. The frequency of the pulse signal is directly proportional to the peak capacitor voltage and the pulse signals are counted to obtain the digital output. In the proposed circuit, the input time interval can be easily controlled and the resolution of the digital output can be improved by controlling the passive devices such as the capacitor and resistor.

A lithium-ion (Li-ion) battery protection IC with an average current of 0.99 µA (at a battery voltage of 3.6 V) and a standby current (after detecting over-discharge) less than 0.01 µA is presented. This low power performance is achieved via a power-on duty-cycle technique. The protection circuit samples the voltage of the battery periodically and powers down during the rest of time. This Li-ion battery protector provides over-charge, over-discharge, excess-current and short circuits protection. This protection IC was implemented in a 0.6-µm CMOS technology and the active area is 880 µm 780 µm.

We have developed 100 nm node CMOS technology, consisting of a 65 nm gate length and a 1.6 nm gate oxide thickness. The major transistor design issue is how to maintain drive current at supply voltage of only 1.0 V, while suppressing standby leakage current to a practical level for system-on-a-chip applications. In order to obtain thinner electrical equivalent oxide thickness with well-suppressed gate leakage current, we have adopted radical nitridation and poly-SiGe. We have also utilized low-energy ion-implantation, low-temperature CVD, and spike RTA technology to overcome the short channel effect. With supply voltage of 1.0 V, our generic transistor shows the drive current of 520/196 µA/µm with the off current of 0.5 nA/µm. We also designed high-speed (Ioff=5 nA/µm), ultrahigh-speed (Ioff=30 nA/µm) transistors, and low-standby power (Ioff=5 pA/µm), all of which can be deployed on the same chip.

A new contention-free Domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional Domino circuits for LVTs are demonstrated using HSPICE(R) simulations and a 0.25 µm CMOS technology with a supply voltage of 2.5 V. The impacts of the new technique on dynamic and leakage powers and area were evaluated. At a 3% area increase, and keeping the noise margins constant, the new CF-DOMINO achieves 20% less delay than conventional DOMINO as the threshold voltage scales from 450 mV down to 200 mV. It also achieved 13% less dynamic power and 5% less leakage at that threshold voltage.

We report our studies on electrical current pulse perturbation of superconducting YBa2Cu3O7-x (YBCO) epitaxial thin films. When a current pulse is applied to a YBCO microbridge, a voltage develops across it that depends on the amplitude of the input current pulse. For a total current (input current pulse plus the dc bias) that is lower than the critical current Ic, an inductive voltage response is observed. When the total current exceeds Ic, a resistive response is generated and is observed after a certain delay time td. The origin of the resistive response was analyzed using the Geier and Schon model, which is based on the time-dependent Ginzburg-Landau equation. Our experimental samples consisted of 200-nm-thick epitaxial YBCO films, patterned into coplanar-strip (CPS) transmission lines, containing either two-microbridge or single-microbridge test structures. For the two-microbridge samples, a train of 100-fs-duration optical pulses was used to excite the larger microbridge and generate 2-ps-duration electrical pulses, which were then applied to perturb the smaller microbridge, which was independently biased in the superconducting state. In this case, an electro-optic sampling system was used to measure the YBCO kinetic-inductive voltage responses with the picosecond time resolution. For the single-microbridge structures, an electronic pulse generator was employed to supply the input current pulse, and a 14-GHz sampling oscilloscope was used to monitor the microbridge responses. The latter signals were in very good agreement with the model of Geier and Schon, assuming that the quasiparticle dynamics process that resulted from the nanosecond-wide current excitation was bolometric and followed the phonon escape time τes.

We present measurements of kilohertz and megahertz sine waves synthesized using a Josephson arbitrary waveform synthesizer. A 4.8 kHz sine wave synthesized using an ac-coupled bias technique is shown to have a stable 121 mV peak voltage and harmonic distortion 101 dB below the fundamental (-101 dBc (carrier)). We also present results of our first phase-noise measurement. A 5.0 MHz sine wave was found to have distortion 33 dB lower than the same signal synthesized using a semiconductor digital code generator. The white-noise floor of the Josephson synthesized signal is -132 dBc/Hz and is limited by the noise floor of the preamplifier.

Recent advances make it possible to mitigate a number of drawbacks of conventional phase locked loops. These advances permit the design of phase tracking system with much improved characteristics that are sought after in modern communication system applications. A new phase tracking system is outlined which reduces the effects of VCO phase noise to an insignificant level. This fact permits extremely narrow bandwidth phase tracking systems to be realized, even when a VCO with poor phase noise characteristics is employed. The improvement in performance over conventional phase locked loops is analyzed. The new phase tracking system also has other benefits such as precise centre frequency and elimination of peaking in the transfer function. To implement the phase tracking system requires a frequency measurement. We outline a new highly integrated frequency measurement method suitable for narrow bandwidth applications. Experimental results from a prototype confirms theoretical results.

A charge pump circuit suitable for positive high voltage generators at sub-1.5 V range is presented. The proposed heap-pump circuit provides a high voltage generator having not only high pumping efficiency by eliminating threshold voltage drop but also simplest single phase clock scheme.

This paper describes 2.4-GHz-band front-end building circuits--a down conversion mixer (DCM), a dual-modulus divide-by-4/5 prescaler, a transmit/receive antenna switch (SW), a power amplifier (PA), and a low noise amplifier (LNA). They are fabricated using a standard bulk 0.18 µm CMOS process with a lower current consumption than bipolar circuits, and can operate at the low supply voltage of 1.8 V. Meshed-shielded pads are adopted for lower receiver circuit noise. Pads shielded by metals become cracked when they are bounded, therefore silicided active areas are used as shields instead of metals to avoid these cracks. The meshed shields achieve lower parasitic pad capacitors without parasitic resistors, and also act as dummy active areas. The proposed DCM has a high IP3 characteristic. The DCM has a cascode FET configuration and LO power is injected into the lower FET. By keeping the drain-source voltage of the upper transistor large, the nonlinearity of the drain-source transconductance is reduced and a low distortion DCM is realized. It achieves a higher input referred IP3 with a higher conversion gain for almost the same current consumption of a conventional single-balanced mixer. The output referred IP3 is higher 5.0 dB than the single-balanced mixer. The proposed dual-modulus prescaler employs a fully-differential technique to achieve stable operation. In order to avoid errors, the fully-differential circuit gives the logic voltage swing margins. In addition, the differential technique also reduces the noise effect from the supply voltage line because of the common-mode signal rejection. The maximum operating frequency is 3.0 GHz, and the one flip-flop power consumption normalized by the maximum operating frequency is 180 µW/GHz.

The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (Vdd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.