This paper reviews analog-circuit researches in the 1990's especially from an academic-side point of view with the aim of pursuing what becomes important in the 21st century. To achieve this aim a large number of articles are surveyed and more than 200 are listed in References.

Channel coding for bandwidth limited channels based on multilevel bit-interleaved channels is discussed in this paper. This coding and decoding structure has the advantage of simplified design, and naturally incorporates flexible and powerful design of unequal error protection (UEP) capabilities, especially over time-varying channels to be often found in mobile radio communications. Multilevel coded modulation with multistage decoding, and bit-interleaved coded modulation are special cases of the proposed general framework. Simulation results verify the usefulness of the system considered.

A 3.3 V CMOS PLL (Phase Locked loop) with a self-feedback VCO (Voltage Controlled Oscillator) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of VCO with a new delay cell. The proposed VCO with a self-feedback path operates at a wide frequency range of 30 MHz-1 GHz with a good linearity. The DC-DC Voltage Up/Down Converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 µm n-well CMOS process. The simulation results illustrate a locking time of 2.6 µsec at 1 GHz, lock in range of 100 MHz-1 GHz, and a power dissipation of 112 mW.

The subject of this study is to propose a new structure that can realize simultaneously high breakdown voltage and high packing density for both Nch low side switch and Pch high side switch in 200 V class rating. As the conventional techniques for the electric field relaxation, the structure of field plate, field ring and RESURF are well known, but these techniques are inadequate for the high packing density because they are the techniques in surface region. In order to conquer this subject, it is necessary to relax the electric field in the deep region. The electric field relaxation was investigated by device simulation. In the Nch low side switch the electric field is relaxed by buried oxide film in SOI structure. However, electric field relaxation cannot be realized only by adapting the SOI structure for Pch high side switch. Then we tried to insert an intrinsic layer between P-drift layer and the buried oxide film in order to spread the depletion layer in the deep region. This spread depletion layer by intrinsic layer and the depletion layer by field plate connect vertically, and the dosage of the ion implantation for drift layer can be set to two times higher than the case without intrinsic layer. As the results, it was revealed that the SOI structure with intrinsic layer is effective to achieve this subject. Furthermore, by fabricating both Nch low side switch and Pch high side switch on intrinsic SOI substrate, breakdown voltage more than 250 V were achieved.

Random modulation refers to the changing of the MOSFET threshold voltage cell by cell. This paper claims it is essential in sub-2-V CMOS design because it reduces the sub-threshold leakage current even in the active and sleep modes as well as in the stand-by mode. We found that a gradated modulation scheme, which gradually changes the ratio of low- Vth cells according to the path-delay, is the best approach. To achieve the minimal leakage current, the way of determining the optimum pair of threshold voltages is also described. Experimental results for microprocessor show that gradated modulation reduces sub-threshold leakage current by 75% to 90% compared to conventional single-low-threshold voltage design without degrading the performance of the circuits.

This paper describes a Variable Threshold-voltage CMOS technology (VTCMOS) which controls the threshold voltage (VTH) by means of substrate bias control. Circuit techniques to combine a switch circuit for an active mode and a pump circuit for a standby mode are presented. Design considerations, such as latch-up immunity and upper limit of reverse substrate bias, are discussed. Experimental results obtained from chips fabricated in a 0.3 µm VTCMOS technology are reported. VTH controllability including temperature dependence and influence on short channel effect, power penalty caused by the control circuit, substrate current dependence at low VTH, and substrate noise influence on circuit performance are investigated. A scaling theory is also presented for use in the discussion of future possibilities and problems involved in this technology.

An 1 V, 50 MHz, 16-bit DSP core was developed using a 0.25-µm Dual Vt library, SRAM, and Mask ROM tailored for 1 V operation. The core speed was 41% enhanced using an alternate MAC and 2-stage execution pipeline. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. An new long wire delay estimation method enhanced the synthesis. The measured power consumption at 0.9 V was 8.7 mW, which was 40% less than the power of the normal library's at 1.3 V, when the PSI-CELP CODEC firmware was run at 40 MHz.

Voltage holding property of liquid crystal (LC) cell for long period was investigated and the experimantal results were analyzed using a microscopic model considered the movement of ions in LC layer. The time dependent voltage decay curve observed in the experiment, which is not driven by the analysis with the conventional equivalent circuit comprised of the capacitance and the resistance, can be well explained by the microscopic model.

This paper describes a novel IDDQ sensor circuit that is driven by only an abnormal IDDQ. The sensor circuit has relatively high sensitivity and can operate at a low supply voltage. Based on a very simple idea, it requires two additional power supplies. It can operate at either 5-V or 3.3-V VDD with the same design. Simulation results show that it can detect a 16-µA abnormal IDDQ at 3.3-V VDD. This sensor circuit causes a smaller voltage drop and smaller performance penalty in the circuit under test than other ones.

In this work, a temperature stable voltage-to-frequency converter (VFC) in which the output frequency is proportional to the input voltage is proposed. The output frequency range is from 22 kHz to 60 kHz and the difference between simulated and calculated values is less than about 5% for this range of output frequency. The temperature variation of sample output frequencies is less than 0.5% in the temperature range -25C to 75C.

New positive and negative bias voltage generators for TFT-LCD's drivers utilizing charge pump circuits are introduced. The generators can generate positive or negative voltages with various amplitude by simply changing the number of pumping stages. By using the circuit simulation program HSPICE, it is demonstrated that the introduced generators can provide enough positive or negative voltages for TFT-LCD's drivers.

At the sliding contact of brush and rotating slip-ring or commutator, it has been recognized that the brush wear is influenced by brush pressure, current density and atmosphere nearby contact part. However, little is known about the relation between brush wear and atmosphere condition in detail. In this paper, the experiments are carried out with a great attention to the effect of surrounding temperature and humidity on brush wear. The sliding part of brush and slip-ring is put on the sealed box and the atmosphere in the sealed box is kept on the specified condition by temperature and humidity control system. The brush wear, contact voltage drop and slip-ring surface morphology are observed after the sliding test. From these results, in both cases of the high humidity (nearby 80%) and low humidity (nearby 20%), the brush wear are large. And the brush wear rate is the lowest around 60% relative humidity. However, the characteristics of brush wear under the 15C is not similar to others. When the surrounding temperature is changed, in case of the 20% humidity, the brush wear increases with increasing surrounding temperature. On the other hand, in case of 80% humidity, the brush wear increases with decreasing surrounding temperature. Consequently, the results clearly shows that the temperature and humidity not only affect the brush wear but also change the condition of the film formation on slip-ring.

In this paper, we investigate multilevel coding and multistage decoding for satellite broadcasting with moderate decoding complexity. An unconventional signal set partitioning is used to achieve unequal error protection capabilities. Two possibilities are shown and analyzed for practical systems: (i) linear block component codes with near optimum decoding, (ii) punctured convolutional component codes with a common trellis structure.

The reorder buffer is usually employed to maintain the instruction execution in the correct order for a superscalar pipeline with out-of-order issue. In this paper, we propose a reorder buffer structure with shelter buffer for out-of-order issue superscalar processors not only to control stagnation efficiently, but also to reduce the buffer size. We can get remarkable performance improvement with only one or two buffers. Simulation results show that if the size of reorder buffer is between 8 and 32, performance gain obtained from the shelter is noticeable. For the shelter buffer of size 4, there is no performance improvement compared to that of size 2, which means that the shelter buffer of size 2 is large enough to handle most of the stagnation. If the shelter buffer of size 2 is employed, we can reduce the reorder buffer by 44% in Whetstone, 50% in FFT, 60% in FM, and 75% in Linpack benchmark program without loss of any throughput. Execution time is also improved by 19.78% in Whetstone, 19.67% in FFT, 23.93% in FM, and 8.65% in Linpack benchmark when the shelter buffer is used.

In this paper, new linearization techniques for low-voltage bipolar OTAs using hyperbolic function circuits are described. First, a design of an exponential-law circuit, which is a basic building block to compose hyperbolic sine and hyperbolic cosine circuits, is proposed. This circuit is simpler than the conventional circuit and is suitable for low-voltage application. Next, two linearized OTAs using the hyperbolic function circuits are presented. The transconductance is given by maximally flat approximation. Although designs of the OTAs are different, the output currents are given by the same expression. Finally, performance of the OTAs is discussed. The linear input voltage range of the proposed OTAs is almost the same as that of the conventional OTA. However, one of the proposed OTA has no more than two-thirds the power dissipation of the conventional one. The other has a superior high-frequency characteristic.

The technique used is based on thermal optical activity measurement of temperature combined with electric-field-induced polarization modulation of the input light. Quartz is used as the sensing element. A 1/4 wave plate is placed behind the quartz so that a single sensing head can simultaneously output two signals: one includes the Pockels effect for voltage measurement; the other optical activity for the temperature measurement. The operating principle of the sensor which detects voltage and temperature is presented theoretically and experimentally. The technique for separating voltage and temperature from the signals is analyzed theoretically and experimentally. It was found that the sensitivity of the voltage sensor to temperature depends on the magnitudes of voltage applied to it. To realize temperature compensation over a full range, two key parameters must be obtained: one is the response of the voltage sensor to temperature when the applied voltage is zero; another is the response of the sensing material to temperature when a certain voltage is applied. In the absence of electrogyration the effect of voltage on the temperature sensor may be neglected. The technique was demonstrated using a fiber-optic voltage sensor with temperature compensation. The sensor offered a voltage measurement range of 0-10 kV, and a temperature stability of 0.4% within the temperature range of 20-70.

This paper reports the performance of an AC-voltage sensor with a LiNbO3 integrated retroreflective structure based on the Y-junction Mach-Zehnder interferometer. This structure is capable of realizing a low-cost sensor chip because of the small chip size and single optical-fiber connection. In the sensitivity and frequency response evaluation, detection sensitivities of 6.3 µ V / Hz have been measured with a frequency response from 6 Hz to 2 GHz. These measurement limitations were also analyzed theoretically and compared with the experimental results. This unique sensor enables precise voltage measurement in an EMI environment, even inside a computer.

In this paper, the suppression of induced voltage on a printed wiring board through impedance loading by inserting impedance devices such as ferrite beads is focused on. How the suppression effect changes according to the insertion position of such devices is also investigated. Electromagnetic-field simulations were used to determine the distribution of voltage and current induced in wiring when a printed wiring board is exposed to an external electromagnetic field. Then, on the basis of these distributions, electromagnetic-field simulations were performed, and experiments were conducted to investigate the relationship between the insertion position of impedance devices and their suppression effect. It was verified that induced voltage can be large when a mismatch occurs between the impedance at the two ends of printed wiring, and that the suppression effect can differ significantly according to where an impedance device is inserted. A large effect was obtained by inserting an impedance device at a point 1/4 wavelength in distance from the end of a wire where voltage is being induced. In addition, comparing the use of resistors with the use of chip ferrite beads as impedance devices revealed similar tendencies in both. The above behavior was confirmed by numerical analysis.

This paper presents a new technique for accurately modeling uni-directional High-Voltage lightly-doped- drain MOS (HV MOS) devices by extending the bi- directional HV MOS model and adopting a new parameter extraction method. We have already reported on a SPICE model for bi-directional HV MOS devices based on BSIM3v3. However, if we apply this bi- directional HV MOS model and its parameter extraction technique directly to uni-directional HV MOS devices, there are large discrepancies between the measured and simulated I-V characteristics of the uni- directional devices. This paper extends the bi- directional HV MOS model, and adopts a new parameter extraction technique. Using parameters extracted with the new method, the simulated I-V characteristics of the uni-directional n-channel HV MOS device match the measured results well. Since our method does not change any model equations of BSIM3v3, it can be applied to any SPICE simulator on which the BSIM3v3 model runs.

This paper describes a method for estimating current and voltage distributions by scanning with a probe. The method takes advantage of the phenomenon that the coupling between the current and the probe varies with the direction of the probe. The current and voltage are estimated by calculating the probe vector output for each of four directions. Both the current and voltage vector distributions can thus be estimated at the same time by using a single probe. The estimated distributions in a digital IC package and a microstrip line showed that this method produces reliable results. The simple structure of the probe should make it easy to reduce its size.