In this research, we investigated the digital/analog-operation utilizing ferroelectric nondoped HfO₂ (FeND-HfO₂) as a blocking layer (BL) in the Hf-based metal/oxide/nitride/oxide/Si (MONOS) nonvolatile memory (NVM), so called FeNOS NVM. The Al/HfN_0.5/HfN_1.1/HfO₂/p-Si(100) FeNOS diodes realized small equivalent oxide thickness (EOT) of 4.5 nm with the density of interface states (D_it) of 5.3 × 10¹⁰ eV^-1cm^-2 which were suitable for high-speed and low-voltage operation. The flat-band voltage (V_FB) was well controlled as 80-100 mV with the input pulses of ±3 V/100 ms controlled by the partial polarization of FeND-HfO₂ BL at each 2-bit state operated by the charge injection with the input pulses of +8 V/1-100 ms.

A reduced dark leakage current, without degrading the near-infrared responsivity, is reported for a vertical pin structure of Ge photodiodes (PDs) on n⁺-Si substrate, which usually shows a leakage current higher than PDs on p⁺-Si. The peripheral/surface leakage, the dominant leakage in PDs on n⁺-Si, is significantly suppressed by globally implanting P⁺ in the i-Si cap layer protecting the fragile surface of i-Ge epitaxial layer before locally implanting B⁺/BF₂⁺ for the top p⁺ region of the pin junction. The P⁺ implantation compensates free holes unintentionally induced due to the Fermi level pinning at the surface/interface of Ge. By preventing the hole conduction from the periphery to the top p⁺ region under a negative/reverse bias, a reduction in the leakage current of PDs on n⁺-Si is realized.

Effects of Al thickness in Ti/Al/Ti/Au ohmic contact on AlGaN/GaN heterostructures are studied. Samples having Al thickness of 30, 90 and 120 nm in Ti/Al/Ti/Au have been investigated by electrical and X-ray photoelectron spectroscopy (XPS) depth profile analysis. It is found that thick Al samples show lower resistance and formation of Al-based alloy under the oxidized Al layer.

This paper introduces a computer-aided low-power design method for tapered buffers that address given load capacitances, output transition times, and source impedances. Cross-voltage-domain tapered buffers involving a low-voltage domain in the frontier stages and a high-voltage domain in the posterior stages are further discussed which breaks the trade-off between the energy dissipation and the driving capability in conventional designs. As an essential circuit block, a dedicated analytical model for the level-shifter is proposed. The energy-optimized tapered buffer design is verified for different source and load conditions in a 180-nm CMOS process. The single-V_DD buffer model achieves an average inaccuracy of 8.65% on the transition loss compared with Spice simulation results. Cross-voltage tapered buffers can be optimized to further remarkably reduce the energy consumption. The study finds wide applications in energy-efficient switching-mode analog applications.

Radiation-induced temporal errors become a significant issue for circuit reliability. We measured the pulse widths of radiation-induced single event transients (SETs) from pMOSFETs and nMOSFETs separately. Test results show that heavy-ion induced SET rates of nMOSFETs were twice as high as those of pMOSFETs and that neutron-induced SETs occurred only in nMOSFETs. It was confirmed that the SET distribution from inverter chains can be estimated using the SET distribution from pMOSFETs and nMOSFETs by considering the difference in load capacitance of the measurement circuits.