In the mid-1990s, ULSI technology will reach Sub-Half-Micron Era and Si chips with 0.30.4 µm design rules will be in the market. The shrinked device size makes it possible to realize a device count of more than 10⁷ and a logic speed of 100200 picosecond per gate. By taking full advantage of these advanced process and device technologies, three basic trends; i.e., (a) higher integration and higher performance, (b) "system-on-chip" or system incorporation onto a single chip, and (c) customization, will be accelerated. Memories will include more logic fuctions on a chip and will become system memories. Microprocessors and ASICs will find a wider variety of applications in data processing, in signal processing and in control. It is prospected definitely that ULSI architecture technology, including system technology and circuit technology, will become more and more important for the progress aiming at the sub-half-micron ULSIs. This paper describes the technology issues that are specific for ULSI memories, microprocessors and ASICs. It overviews technology issues that are common to various ULSI chips, covering design, test, fault-tolerant technique, packaging, and high-speed device circuit. A few of future technological issues, such as Cryo-CMOS/BiCMOS and neural network, are briefly discussed with regard to their potentials as the new elements in ULSI architecture.

Recent advances in VLSI memories have enabled integration of 10 to 30 million devices on prototype chips for 16 Mbit DRAMs, 16 Mbit EPROMs, and 4 Mbit SRAMs. An experimental 64 Mbit DRAM recently reported clearly shows that an integration density of more than 100 million devices on a chip will be feasible in the near future. These advances have been made not only by progress in fine processing technology, but also by the development of three-dimensional memory cells such as trench capacitor cells and stacked capacitor cells for DRAMs and polysilicon PMOS load cells for SRAMs. Various circuit innovations to increase the signal-to-noise ratio and circuit speed have been, and will continue to be, essential. Future circuits will be required to operate at very low voltages, and the prototype 64 Mbit DRAM has shown that an operating voltage as low as 1.5 volts is feasible. Improvements in packaging technology for reducing package volume and footprint area, as well as for production of multipackage modules, are also becoming more and more important.

The advances in silicon IC technology have provided an incredible performance increase in MPU developments. This paper describes that history of microprocessor developments, as well as future direction of MPU developments from the viewpoint of architectural design. Also, an empirical study of the development shows that changes of MPU generation occurs every four years with rapid performance increase between generations.

Focusing on gate array and standard cell design LSIs, technology trends in ASIC are discussed. MOS transistors with LDD or modified LDD structures will be effective down to around 0.4 µm. Upon further miniaturization, simple single-drain structure MOS transistors will become prominent. SOI-structure MOS transistors may be even more effective with a smaller short channel effect. The supply voltage should be lowered to 3.3 V for 0.5 µm CMOS LSIs to decrease power dissipation owing to the increase of gate count and operation speed. SOG gate arrays will increase their share of the ASIC market. BiNMOS circuits will be useful under 5 V VDD condition. However, below 3.0 V, CMOS circuits will be preferable. In the near future, tpd of 20-30 ps/gate and 40-50 ps/gate should be attained for GaAs FET and Si-bipolar LSIs, respectively.

Time transient scattering field dur to a line source located at the center of the dielectric cylinder has been calculated. In the analysis, the corresponding time harmonic result has been formulated first rigorously, then the high frequency asymptotic expansion result has been derived. Thus obtained result is found to coincide wiht the one constructed directly by ray approximation. Fourier invesion for an impulsive response has been done by two methods, namely the Singularity Expansion Method and wavefront expansion method. While the former method collects the contributions around the singularities in the complex frequency domain, the latter gives us a result which is a summation of each successive wavefront arrivals. A finite Hilbert transform technique has been introduced to recover the causal responses of odd-time caustic passing wavefronts. Also derived are results of numerical inversion by Fast Fourier Transform Technique for the frequency band limited incident pulses. A Gaussian pulse has been introduced to simulate an impulse response result, and a raised cosine pulse which de-emphasizes the low frequency defects of asymptotically constructed frequency spectrum confirms the usefulness of ray solution.

A simple method for calculating the optimum transit angles of QWITT diodes is proposed. The carrier diffusion effect and the drift velocity transient effect in QWITT diodes are considered. Reasonably good agreement between our results and those by a more rigorous analysis is obtained.