A semi-analytical approach for analyzing the electromagnetic radiation of a line source in cylindrical electromagnetic bandgap (EBG) structure is presented. The cylindrical structure is composed of circular rods periodically distributed along concentrically layered circular rings. The method uses the T-matrix of a circular rod in isolation, the reflection and transmission matrices of a cylindrical array expressed in terms of the cylindrical waves as the basis, and the generalized reflection and transmission matrices for a layered cylindrical structure. Using the proposed method, the radiated field from a line source placed inside a three-layered cylindrical EBG structure with defects is investigated. The defects are created by removing the particular circular rods from each circular ring. The structure is prominent from the viewpoint of flexible design of the directive antennas. Numerical examples demonstrate that the cylindrical EBG structures are very effective at forming and controlling the directed beam in the radiated fields.

A detailed analysis of a multilayer symmetric coupler employing symmetrical broad-side coupled lines is presented. We confirm that the coupler can be designed using a well-known even-odd mode analysis of two strip lines while the coupler has four strip lines. We also confirm that the previously reported poor isolation originates from port mismatching. To verify the analysis, couplers that have different dimensions are fabricated. One example exhibits a coupling loss of 4.50.5 dB, a return loss better than 15 dB, and isolation characteristics higher than 12 dB in the 6.5 to 15.1 GHz frequency range. These results agree well with the obtained simulation results. The results show that the coupler has the potential to provide tight and ideal coupling.

The Noise Shaper of a full digital amplifier overflows randomly when the Modulation Index of PWM is higher than a certain value. The clipping from the overflow produces an abrupt increase of THD+N that limits MI or the maximum output power. In this paper, we discussed the reason of NS overflow and derived the critical value of MI. We proposed a compensation method for the clipping error and optimized compensation in the audio band. The measurement results show that the proposed method can increase the maximum output power by 6.4% at a 1% THD+N condition. The compensation is more important where the power supply voltage and speaker impedance are difficult to change as that in a car stereo or mobile.

This paper presents a new low-dropout (LDO) regulator with low-quiescent, high-drive and fast-transient performance. This is based on a new composite power transistor composed of a shunt feedback class-AB embedded gain stage and the application of dynamic-biasing schemes to both the error amplifier as well as the composite power transistor. The proposed LDO regulator has been simulated and validated using BSIM3 models and GLOBALFOUNDRIES 0.18-µm CMOS process. The simulation results have shown that the LDO regulator consumes 4.7 µA quiescent current at no load, regulating the output at 1 V from a minimum 1.2 V supply. It is able to deliver up to 450 mA load current with a dropout of 200 mV. It can be stabilized using a 4.7 µF output capacitor with a 0.1 Ω ESR resistor. The maximum transient output voltage is 64.6 mV on the basis of a load step change of 450 mA/10 ns under typical condition. The full load transient response is less than 350 ns.

This work describes a 12-bit 100 MS/s 0.13 µm CMOS three-stage pipeline ADC with various circuit design techniques to reduce power and die area. Digitally controlled timing delay and gate-bootstrapping circuits improve the linearity and sampling time mismatch of the SHA-free input network composed of an MDAC and a FLASH ADC. A single two-stage switched op-amp is shared between adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs based on slightly overlapped switching clocks. The interpolation, open-loop offset sampling, and two-step reference selection schemes for a back-end 6-bit flash ADC reduce both power consumption and chip area drastically compared to the conventional 6-bit flash ADCs. The prototype ADC in a 0.13 µm CMOS process demonstrates measured differential and integral non-linearities within 0.44LSB and 1.54LSB, respectively. The ADC shows a maximum SNDR and SFDR of 60.5 dB and 71.2 dB at 100 MS/s, respectively. The ADC with an active die area of 0.92 mm² consumes 19 mW at 100 MS/s from a 1.0 V supply. The measured FOM is 0.22 pJ/conversion-step.

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98 dBc/Hz. The locking range of the PLL is from 22.6 GHz to 23.3 GHz and the reference spur level is -69 dBm that is 54 dB bellow the carrier. The power consumption is 9.2 mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

With exponentially increasing power densities due to technology scaling and ever increasing demand for performance, chip temperature has become an important issue that limits the performance of computer systems. Typically, it is essential to use a set of on-chip thermal sensors to monitor temperatures during the runtime. The runtime thermal measurements are then employed by dynamic thermal management techniques to manage chip performance appropriately. In this paper, we propose an inverse distance weighting method based on a dynamic Voronoi diagram for the reconstruction of full thermal characterization of integrated circuits with non-uniform thermal sensor placements. Firstly we utilize the proposed method to transform the non-uniformly spaced samples to virtual uniformly spaced data. Then we apply three classical interpolation algorithms to reconstruct the full thermal signals in the uniformly spaced samples mode. To evaluate the effectiveness of our method, we develop an experiment for reconstructing full thermal status of a 16-core processor. Experimental results show that the proposed method significantly outperforms spectral analysis techniques, and can obtain full thermal characterization with an average absolute error of 1.72% using 9 thermal sensors per core.

This paper presents a content-addressable memory (CAM) using a phase-change device. A hierarchical match-line structure and a one-hot-spot block code are indispensable to suppress the resistance ratio of the phase-change device and the area overhead of match detectors. As a result, an 8-nsec 72-bit-parallel-search CAM is implemented using a phase-change-device/MOS-hybrid circuitry, where high and low resistances are higher than 2.3 MΩ and lower than 97 kΩ, respectively, while maintaining one-day retention.

This paper presents the design consideration of a four-stage variable gain amplifier (VGA) with a wide dynamic range for receivers. The VGA uses parallel amplifiers for the first and second amplifiers in order to improve the input third-order intercept point (IIP3) in the low gain region. To investigate the behavior of the VGA, the gain and linearity analyses are newly derived for the parallel amplifiers, and are compared with the measured results. In addition, the principle of the temperature compensation is described. The gain control range of 110 dB, the IP1 dB of -11 dBm, and noise figure (NF) of 5.1 dB were measured using a 0.5 µm 26 GHz f_T BiCMOS process.

The applicability in harsh optical environments, such as dark smog, or strong backlight of ultra-wide band (UWB) pulse radar has a definite advantage over optical ranging techniques. We have already proposed the extended Synthetic Aperture Radar (SAR) algorithm employing double scattered waves, which aimed at enhancing the reconstructible region of the target boundary including shadow region. However, it still suffers from the shadow area for the target that has a sharp inclination or deep concave boundary, because it assumes a mono-static model, whose real aperture size is, in general, small. To resolve this issue, this study proposes an extension algorithm of the double scattered SAR based on a multi-static configuration. While this extension is quite simple, the effectiveness of the proposed method is nontrivial with regard to the expansion of the imaging range. The results from numerical simulations verify that our method significantly enhances the visible range of the target surfaces without a priori knowledge of the target shapes or any preliminary observation of its surroundings.

This paper presents a current-reused quadrature voltage-controlled oscillator (QVCO) which adopts a source-connection coupling structure. The QVCO simultaneously achieves low phase noise and low power consumption by newly combining current-reused VCOs and coupling transistors. The measured QVCO obtains good FoM of -188.2 dBc at a frequency of 2.2 GHz with 3.96 mW power consumption.

This paper proposes an active-RC filter that achieves a wide pseudo-continuous bandwidth-tuning range and a wide gain range with fine steps using a novel switched resistor architecture. A channel-selection filter with the proposed resistor bank is designed for a multi-mode mobile-TV receiver with the 6th order Chebyshev-I topology. The bandwidth, 0.5–6 MHz with 5% steps, supports multiple mobile-TV standards with sufficient margins for process and temperature variations. The filter also accomplishes a 30-dB variable gain range with 6-dB steps, and it relaxes the dynamic range requirement of a succeeding programmable gain amplifier. The power consumption of the filter, 3.4–5.0 mW, is adjustable according to the bandwidth and the signal level. The filter was fabricated with on-chip bandwidth-calibration circuitry in 0.18-µm CMOS and occupied 0.81 mm².

A novel divide-by-3 injection-locked frequency divider (ILFD) is proposed. The ILFD circuit is realized with a cross-coupled n-core MOS LC-tank oscillator embedded with a push-push signal generator and two injection MOSFETs for coupling the injection signal into the resonator. The ILFD uses the linear mixer to extend the locking range and has been implemented in a standard 0.18 µm CMOS process. The core power consumption of the ILFD core is 3.12 mW. The divider's free-running frequency is tunable from 4.26 GHz to 4.9 GHz by tuning the varactor's control bias, and at the incident power of 0 dBm the locking range of the ILFD used as a divide-by-3 divider is 1.5 GHz, from 12.5 GHz to 14.0 GHz.

A dual-band divide-by-2 quadrature injection-locked frequency divider (QILFD) is proposed to achieve high-speed, low power, wide-locking range, and accurate quadrature output phases. The QILFD consists of two dual-resonance differential voltage controlled oscillators and four coupling NMOS injectors in a ring configuration. The injectors are used as coupling devices of two differential ILFDs and are also used as common source amplifiers. The proposed QILFD has been implemented with the TSMC 90 nm CMOS technology and the core power consumption is 2.31 mW at the dc drain-source bias of 0.5 V. At the input power of 0 dBm, the low-band and high-band divide-by-2 operation ranges are respectively from 7.0 GHz to 10.1 GHz and 19.8 GHz to 24.6 GHz.

This paper presents a technique to enhance in-band mismatch noise reduction of multi-stage second order Dynamic Element Matching (DEM) in multi-level ΔΣ Digital-to-Analog Converters (DACs). The presented technique changes an operational behavior of multi-stage DEM to reduce mismatch noise at in-band frequency. This change improves mismatch noise shaping performance for small amplitude input signals. Simulation result using 2-stage second order DEM and a third order 17-level ΔΣ modulator with 0.5% analog element mismatch shows 3.4 dB dynamic range improvement.

This paper proposes a built-in self-test (BIST) scheme for noise-tolerant testing of a digital-to-analogue converter (DAC). The proposed BIST calculates the differences in output voltages between a DAC and test modules. These differences are used as the inputs of an integrator that determines integral nonlinearity (INL). The proposed method has an advantage of random noise cancelation and achieves a higher test accuracy than do the conventional BIST methods. The simulation results show high standard noise-immunity and fault coverage for the proposed method.