The front-end LSI having a capable of 2 reading and writing of BD-R/RW/ROM is developed. Its readability is improved by adopting 5-tap adaptive partial response maximum likelihood (PRML) with the PR(a,b,c,d,e) type channel. Due to the proposed PRML, less than 210-4 of the bit error rate (BER) is achieved with radial and tangential tilt margin of over 0.6°on 25 GB disc. The method of an optimum power control (OPC) for stable writing of various BD-R/RW is proposed. The presented chip contains 14-million transistors in a 60 mm2 dies, and is fabricated in 0.18 µm CMOS technology.

To drastically reduce the power dissipation (P) of an absolute difference accumulation (ADA) circuit for H.26x/MPEG4 motion estimation, a fast block-matching (BM) algorithm called the Multiple Block-matching Step (MBS) algorithm has been developed. The MBS algorithm can drastically improve the block matching speed, while achieving the same visual quality as that of a full search (FS) BM algorithm. Power dissipation (P) of a 0.18-µm CMOS absolute difference accumulator (ADA) circuit employing the MBS algorithm is significantly reduced to the range of about 0.3% to 12% that of the same ADA circuit adopting FS.

For more efficient data transmissions, a new MLP/BP-based channel equalizer is proposed to compensate for multi-path fading in wireless applications. In this work, for better system performance, we apply the soft output and the soft feedback structure as well as the soft decision channel decoding. Moreover, to improve packet error rate (PER) and bit error rate (BER), we search for the optimal scaling factor of the transfer function in the output layer of the MLP/BP neural networks and add small random disturbances to the training data. As compared with the conventional MLP/BP-based DFEs and the soft output MLP/BP-based DFEs, the proposed MLP/BP-based soft DFEs under multi-path fading channels can improve over 3-0.6 dB at PER=10-1 and over 3.3-0.8 dB at BER=10-3.

Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

This paper presents sector based flooding (SBF) and adaptive sector-based flooding (ASBF) that are flooding methods for mobile ad hoc networks using position information. SBF, which divides the communication area of a sender node into sectors, allows only the node nearest to a sector representative position in each sector to rebroadcast a packet. SBF is divided into two methods, SBF-1 and SBF-2; the difference is the number of criteria used to decide whether to rebroadcast or to drop the packet. In ASBF, each node selects a flooding method from among SBF-1, SBF-2, and pure flooding, depending on its local node density. The node density is obtained from the distance between the sector representative position and its nearest node. Simulation results show that SBF reduces the number of packet transmissions generated in flooding and ASBF has high packet reachability with few packet transmissions.

This paper proposes a novel signal estimation method that uses a tensor product expansion. When a bivariable function, which is expressed by two-dimensional matrix, is subjected to conventional tensor product expansion, two single variable functions are calculated by minimizing the mean square error between the input vector and its outer product. A tensor product expansion is useful for feature extraction and signal compression, however, it is difficult to separate global noise from other signals. This paper shows that global noise, which is observed in almost all input signals, can be estimated by using a tensor product expansion where absolute error is used as the error function.

Based on the channel properties of of the meteor burst communication, a kind of semi-irregular LDPC codes suitable for MBC is presented. Simulation results show that the application of this kind of semi-irregular LDPC codes in MBC yields better performance than the regular ones. Some theoretical analyses are given.

An opamp design with outside-rail output relaxing a low-voltage constraint on future scaled transistors is presented. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8-V 0.18-µm standard CMOS process. The 3-V-output operation is experimentally verified. The outside-rail output design with scaled transistors shows area advantage over un-scaled and inside-rail design while keeping signal-to-noise ratio and gain bandwidth constant. The chip area is estimated to be 47% of the conventional opamp using a 0.35-µm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-µm CMOS design due to reduced capacitor area. The proposed design could be extended to n-tuple VDD operation and applied to circuits with a feed back loop such as gain stage and filters. The extendibility of n-tuple VDD operation and its application are discussed with simulation results.

This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25 µm 4-metal process technology.

A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.

Recently, self-reconfigurable devices which can be partially reprogrammed by other part of the same device have been proposed. However, since conventional self-reconfigurable devices are LUT-array-based fine-grained devices, their time efficiency is spoiled by overhead for reconfiguration time to load large amount of configuration data. Therefore, we have to improve architectures. At the architecture design phase, it is difficult to estimate the performance, including reconfiguration overhead, of self-reconfigurable devices by static analysis, since it depends on many architecture parameters and unpredictable run-time behavior. In this paper, we propose a simulation-based platform for design exploration of self-reconfigurable devices. As a demonstration of the proposed platform, we implement an adaptive load distribution model on the devices of various reconfiguration granularities and evaluate performance of the devices.

A fully integrated broadband up-conversion mixer with low power consumption is demonstrated on 90 nm CMOS technology in this paper. This mixer has a single-ended input and a multi-layer stacked Marchand balun is used for converting the differential output of the single-balanced mixer topology to a single-ended output. This balun employs inductive coupling between two metal layers and includes slotted shields to reduce substrate losses. The circuit size is 650 µm570 µm. At 22.1 GHz, the integrated mixer achieves a conversion gain of 2 dB with a maximum power dissipation of only 11.1 mW from a 1.2 V dc power supply at LO power of 5 dBm. Input referred 1-dB compression point is -14.8 dBm. The LO and RF return loss are better than 10 dB for frequencies between 20-26 GHz.

With the recent advance of process technology shrinking, process parameter variation has become one of the major issues in SoC designs, especially for timing convergence. Recently, Statistical Static Timing Analysis (SSTA) has been proposed as a promising solution to consider the process parameter variation but it has not been widely used yet. For estimating the delay yield, designers have to know and understand the accuracy of SSTA. However, the accuracy has not been thoroughly studied from a practical point of view. This paper proposes two metrics to measure the pessimism/optimism of SSTA; the first corresponds to yield estimation error, and the second examines delay estimation error. We apply the metrics for a problem which has been widely discussed in SSTA community, that is, normal-distribution approximation of max operation. We also apply the proposed metrics for benchmark circuits and discuss about a potential problem originating from normal-distribution approximation. Our metrics indicate that the appropriateness of the approximation depends on not only given input distributions but also the target yield of the product, which is an important message for SSTA users.

This paper proposes a maximum likelihood sequence estimation (MLSE) for the differential space-time block code (DSTBC) in cooperation with blind linear prediction (BLP) of fast frequency-flat fading channels. This method that linearly predicts the fading complex envelope derives its linear prediction coefficients by the method of Lagrange multipliers, and does not require data of decision-feedback or information on the channel parameters such as the maximum Doppler frequency in contrast to conventional ones. Computer simulations under fast fading conditions demonstrate that the proposed method with an appropriate degree of polynomial approximation is superior in BER performance to the conventional method that estimates the coefficients by the RLS algorithm using a training sequence.

Recently, research on parallel processing systems is very active, and many complex topologies have been proposed. A burnt pancake graph is one such topology. In this paper, we prove that a faulty burnt pancake graph with degree n has a fault-free Hamiltonian cycle if the number of the faulty elements is n-2 or less, and it has a fault-free Hamiltonian path between any pair of nonfaulty nodes if the number of the faulty elements is n-3 or less.

A method for shortening of the settling time in all digital phase-locked loops is proposed. The method utilizes self monitoring to obtain the parameters necessary for feed-forward compensation. Analysis shows that by employing this technique both fast settling and good stability can be achieved simultaneously. Matlab and Verilog-AMS simulation shows that typical settling speed can be reduced to less than one tenth compared to a system without the feed-forward compensation, by merely employing the feed-forward compensation system. Further more a design example shows that this settling time can be decreased further to less than one fifteenth through design considerations when compared to a speed optimized phase-locked loop design system without direct reference feed-forward compensation.

Geographic distributed hash table (DHT) protocols are considered to be efficient for P2P object sharing in mobile ad-hoc networks. These protocols assume that the set of pairs, called indexes, should be distributed among nodes according to the following hashing mapping rule: A key hashes into a geographic coordinate, and the corresponding index is stored at the node closest to the key's hash value. Therefore, when a node changes its position, some indexes have to be redistributed to other nodes in order to keep the hashing mapping rule consistent. The overhead of index redistribution may be high enough to impact the normal lookup operation if each node contains a large number of indexes. In this paper, we propose an efficient lookup protocol, called Double Indirect Access, that dispenses with index redistribution to improve lookup performance. The main idea is to determine the mapping from an index to a node not by the node's position, but by the node's static identifier that is obtained by hashing its MAC address into a geographic coordinate. However, a key lookup request will be routed to some node based on the key's hash value, resulting in failure of locating the index. In Double Indirect Access, the node to which a key lookup request has been routed is named as an indirection server, and it is responsible for relaying the lookup request to the node storing the corresponding index. In order for the indirection server to find out the correct destination node for the lookup request, it maintains a list of nodes' static identifiers whose values (i.e., geographic coordinates) are close to the location of the indirection server. Simulation results show that, when the average number of objects per node is more than 256, our approach is able to reduce the number of packet transmissions by about a half compared to the conventional geographical DHT protocol. It is also shown that, even when the average number of objects per node is about 9-16, the overhead of our approach is comparable with the conventional protocol.

Business Processes are considered a crucial issue by many enterprises because they are the key to maintain competitiveness. Moreover, business processes are important for software developers, since they can capture from them the necessary requirements for software design and creation. Besides, business process modeling is the center for conducting and improving how the business is operated. Security is important for business performance, but traditionally, it is considered after the business processes definition. Empirical studies show that, at the business process level, customers, end users, and business analysts are able to express their security needs. In this work, we will present a proposal aimed at integrating security requirements through business process modeling. We will summarize our Business Process Modeling Notation extension for modeling secure business process through Business Process Diagrams, and we will apply this approach to a typical health-care business process.

In this paper, we examine the Interleaved Polling with Adaptive Cycle Time (IPACT) that was proposed to control upstream traffic for Gigabit Ethernet-PONs, a promising technology for the Fiber To The Home (FTTH). We analyzed the performance for the gated service and the limited service mathematically. To do this, the IPACT protocol was modeled as a polling system and analyzed by using mean-value analysis technique. The traffic arrival rate λ was divided into three regions, and each region was analyzed separately and merged appropriately by using an interpolation method. The average packet delay, average queue size, and average cycle time of both the gated service and the limited service were obtained through the analysis. In order to evaluate the accuracy of the mathematical analysis, discrete event simulation was performed for the IPACT protocol. Simulation results show the accuracy of the mathematical analysis. The analysis results can be widely used in the design of the FTTH system based on EPON, as the performance results in the present study can be obtained in a rather short time. We can design an appropriate system depending on various traffic conditions by adjusting system parameters, such as the number of users N, the maximum transfer window WMAX, and so on.

Many embedded system application in ubiquitous network strongly require the high performance SoC with overcoming the physical limitations in the advanced CMOS. To develop these SoC, the continuous design efforts have been done. The initial efforts are the primitive level circuit technique and power switching control method for suppressing the standby currents. However, the additional physical limitations and system enhancements becomes main factors, the new design efforts have been proposed. These design efforts are the application-oriented technologies from the system level to device level. This paper introduces the self voltage controlled technique to cancel the PVT (process, voltage, and temperature) variation, power distribution and power management for cellular phone application, parallel algorithm and optimized layout DSP, and massively parallel fine-grained SIMD processor for next multimedia application. The high performance SoC for the embedded are achieved by providing the components of the system level IPs and making the application oriented SoC platform.