The transfer characteristic of an integrator is affected by excess-phase shift caused by the parasitic capacitance. The phase compensation is obtained by introducing zeros to generate phase lead. This paper proposes a phase compensation technique for the differential signal input integrator. The proposed technique is employing feedforward signal current source. The fifth-order leapfrog Chebyshev low-pass filter with 0.5 dB passband ripple is designed using the integrator with the proposed phase compensation. Further, an autotuning phase compensation system using the proposed technique is realized by applying a PLL system. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator with the proposed phase compensation shows that excess-phase cancellation is obtained at various unity gain frequencies. The accurate filter characteristic of the fifth-order leapfrog filter is obtained by using the autotuning phase compensation system. The passband of the filter is improved over wide range of frequencies. The proposed technique is suitable for low voltage application.

This paper proposes design of new linear bipolar OTAs using hyperbolic circuits with an intermediate voltage terminal. Four types of the OTAs are presented; two OTAs contain a hyperbolic sine circuit and the other two OTAs employ a hyperbolic cosine circuit. The linear input voltage range of the proposed OTAs is wider than that of the well-known conventional OTA, multi-TANH doublet, while each proposed OTA has advantages, such as low power dissipation, high-frequency characteristics and so on. The results of SPICE simulation show that satisfactory characteristics are obtained.

A DC-DC converter using two transformers is proposed. One transformer delivers the energy to a load when a switch is on and the other transfers the flyback energy to a load when a switch is off. The primary windings of the two transformers function as choke inductance alternately, and thus the output voltage control by means of the duty ratio and the zero-voltage-switching are possible without an additional inductor. The breadboarded prototypes of the single output and the two outputs have confirmed the principles of operation and demonstrated the high conversion efficiency.

With the progress of integration of circuits and PCBs (Printed Circuit Boards), novel techniques have been required for verification of signal integrity. Noise analysis of the power/ground planes is one of the most important issues. This paper describes a high-speed simulator for PCBs which contain the interconnects with nonlinear terminations. This simulator is based on the environmental tool ASSIST (Assistant System for Simulation Study) constructed for development of the circuit simulators, and is combined with PRIMA (Passive Reduced-Order Interconnect Macromodeling Algorithm). In this simulator, an efficient implementation of PRIMA is considered with using a voltage-controlled current source (VCCS) model. Finally, this simulator is applied to the analysis of power/ground planes of the simple PCBs, and the validity is verified.

Associative memories composed of sparsely interconnected neural networks (SINNs) are suitable for analog hardware implementation. However, the sparsely interconnected structure also gives rise to a decrease in the capability of SINNs for associative memories. Although this problem can be solved by increasing the number of interconnections, the hardware cost goes up rapidly. Therefore, we propose associative memories consisting of multilayer perceptrons (MLPs) with 3-valued weights and SINNs. It is expected that such MLPs can be realized at a lower cost than increasing interconnections in SINNs and can give each neuron in SINNs the global information of an input pattern to improve the storage capacity. Finally, it is confirmed by simulations that our proposed associative memories have good performance.

It have been one open and significant topic for real-time applications to enhance the processing-speed of Boltzmann machines for long time. One effective way of solution of this problem is the augmentation of probability of neurons' state move. In this paper, a novel method, called a rejectionless method, was proposed and introduced into the Boltzmann machines for this augmentation. This method has a feature of independence on the ratio of neurons' state move. The efficiency of this method for speed-up was confirmed with the experiments of TSP and graph problem.

Many researches have been conducted on the recognition of Thai characters. Different approaches, such as neural network, syntactic, and structural methods, have been proposed. However, the success in recognizing Thai characters is still limited, compared to English characters. This paper proposes an approach to recognize the printed Thai characters using the hybrid of global feature, local features, fuzzy membership function and the neural network. The global feature classifies all characters into seven main groups. Then the local features and the neural network are applied to identify the characters.

A new four-quadrant (4Q) Multiplier complementally using linear and saturation regions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is proposed for the wide dynamic range and superior flexibility of the input range. This multiplier operates in the region except for the threshold voltage V_T to zero. The validity of the proposed circuit is confirmed through HSPICE simulation.

An LMS adaptive digital filter using distributed arithmetic (DA-ADF) has been proposed. Cowan and others proposed the DA adaptive algorithm with offset binary coding for the simple derivation of an algorithm and the use of an odd-symmetry property of adaptive function space (AFS). However, we indicated that a convergence speed of this DA adaptive algorithm degraded extremely by our computer simulations. To overcome these problems, we have proposed the DA adaptive algorithm generalized with two's complement representation and effective architectures. Our DA-ADF has performances of a high speed, small output latency, a good convergence speed, small-scale hardware and lower power dissipation for higher order, simultaneously. In this paper, we analyze a convergence condition of DA adaptive algorithm that has never been considered theoretically. From this analysis, we indicate that the convergence speed is depended on a distribution of eigenvalues of an auto-correlation matrix of an extended input signal vector . Furthermore, we obtain the eigenvalues theoretically. As a result, we clearly show that our DA-ADF has an advantage of the conventional DA-ADF in the convergence speed.

Traditional watermarking methods based on spectrum manipulation use watermark bit as a colored noise. However, those methods show poor robustness for filtering and audio compression because of only a few spectrum coefficients being modified. In this paper, we propose a new algorithm for robust audio watermarking by using spectrum warping. Our watermark-embedding scheme is not based on spectrum coefficient manipulation, but based on warping spectrum that shifts a block of spectrum coefficients nonlinearly. The host audio signal is divided appropriately into small segments and then a non-orthogonal transform, such as bi-linear transform, is used for each segment to embed as well as to extract watermarks. Because the proposed scheme uses small segment length, we can afford to embed signature information many times into audio signal without severe degradation of SNR. Our multiple embedding scheme increases robustness against abnormal distortion of watermarked signal and has no bit error rate in MPEG1 Layer-3 128 kbps and 96 kbps compression as well as low/high pass filtering.

This paper proposes a fast method for the calculation of exponential B-splines sampled at regular intervals. This algorithm is based on a combination of FIR and IIR filters which enables a fast decomposition and reconstruction of a signal. When complex values are selected for the parameters of the exponentials, complex trigonometric functions are obtained. Only the real part of these functions are used for the interpolation of real signals, leading less bandlimited signals when they are compared with the polynomial B-spline counterparts. These characteristics were verified with 1-D and 2-D examples. This paper also discusses the effectiveness of exponential B-splines, when they are applied to image processing.

This paper deals with two-processor nonpreemptive scheduling problem for acyclic SWITCH-less program nets including two types of nodes: AND-node and OR-node. Compared with task graphs that are a special case of acyclic SWITCH-less program nets and include only AND-nodes, the multiprocessor scheduling problem of general acyclic SWITCH-less program nets is more complicated. Since multiprocessor scheduling problem for general task graphs is NP-hard, so is for acyclic SWITCH-less program nets generally. In this paper, we suppose the acyclic SWITCH-less program nets satisfy: (i) each AND-node and OR-node have 1 and 0 node firing time, respectively; (ii) each AND-node possesses single input edge. For such a class of acyclic SWITCH-less program nets, we first propose a hybrid priority list L that consists of both dynamic and static sub-lists. Then we prove that, for a given acyclic SWITCH-less program net to be executed by two identical processors, the schedule generated by L is optimal.

This paper describes a new approach to the digital watermarking of motion pictures dedicatedly for the MPEG-4 video coding, which intends to enhance the error detection ability. The conventional method lacks not only the detection ability but also the compatibility with video decoders widely used today. Thus in this approach the digital watermarks are to be embedded into the quantized DCT (Discrete Cosine Transform) coefficients for the error detection, where the prevention of the picture quality degradation is also attempted. Experimental results are shown to demonstrate that the error detection ability of the proposed approach is significantly improved, as compared with that of the conventional method, and that the degradation of the picture quality by the watermarking is extremely small.

In this paper, the forward link erlang capacity and outage probability for hierarchical cellular system based on 2 layer macrocell/microcell are derived analytically by considering the impact of imperfect power control and soft hand-off. The analysis on the outage probability is carried out using two methods: lognormal approximation and Chernoff upper bound. We assume that voice and multi-rate data service users are distributed uniformly in each cell and the same spectrum is applied in both layers. In addition, we take into account the base station transmission power ratio between tiers and the relative position of microcell having island distribution in macrocell. The forward link interference is evaluated by using Monte-Carlo simulation introduced in [2]. In this paper, we compare the forward link erlang capacity of 1x system to 3x system and show that 3x system can increase the user capacity by 3.4 times in case of macrocell and microcell, respectively, compared to 1x system.

We consider the services of broadcasting short messages via forward signaling channels in wireless cellular networks. In the provision of such services, the negative effect of short messages on the delivery of delay-sensitive control messages must be restricted. On the other hand, it is desirable to accommodate the users' demands for service enhancements involving timeliness and informativeness. As a way to resolve such conflicting arguments, we present a generic scheme in which a short message may be rejected or removed according to the buffer occupancy at the base station and is split into a number of segments for the transmission across a forward signaling channel. However, the rejection, removal and segmentation exhibit a trade-off among several facets of service enhancements. Thus, for a quantitative evaluation of the scheme and efficient optimization of design parameters, we develop an analytical method to calculate the moments of delay times experienced by control and short messages at a base station. Using the analytical method, we investigate the delay and loss performance of control and short messages with respect to the message load and short message length.

A new MAC protocol using the Adaptive Weighted Round Robin with Delay Tolerance (AWRR/DT) is presented. The proposed protocol is a type of centralized MAC protocol where the base station performs most operations. By using the AWRR/DT scheduler, we can guarantee delay QoS to different traffics without the heavy overhead induced by packet-based tagging techniques. In order to enhance the efficiency of random access systems, the proposed protocol employs three novel contention methods: slotted ALOHA with threshold, contention method using adaptive contention period, and traffic-specific contention method. Simulation results show that the proposed protocol guarantees delay bounds by using the AWRR/DT. The slotted ALOHA with threshold suffers less collisions than the regular slotted ALOHA when mobile terminals request slots. The method using adaptive contention period adjusts the length of contention period of each frame to relieve the performance degradation by collisions. The traffic-specific contention method provides a priority handling mechanism to contention-based systems. Experimental results of each contention method are provided.

The multicast ATM switch has been developed for the purpose of the point-to-multipoint cell transmission. The basic structure of conventional multicast ATM switches is mainly based on a T. T. Lee's multicast switch, since it has a very simple and expandable structure. However, in spite of these benefits, it requires excessive hardware for the loss-free cell transmission, since it employs the blocking network, i.e., the banyan network as a copy network and a routing network. In this paper, we propose a new network for the multicast ATM switching. In proposed copy network, we adopt a new structure, the parallel broadcast banyan network with bypass links between switch planes, to offer the maximum cell transmission capacity and the fault tolerance. All conflict cells, which are blocked during the cell routing process, are bypassed to the next switch plane through bypass links and try to be routed. And to support the highly efficient cell transmission, we propose Alternate Path Scheme (APS) and copy-number (CN) comparator in the proposed copy network. APS is a kind of cell transmission schemes and guarantees multicasting capability to achieve a high performance. To estimate the performance of a proposed copy network, we provide several simulation results.

Nonlinear feedback shift registers (NFSRs), which can generate maximal-period sequences called de Bruijn sequences, are regarded as one-dimensional maps with finite bits by observing states of the registers at each time. Such one-dimensional maps are similar to the Bernoulli map which is a famous chaotic map. This implies that an NFSR is one of finite-word-length approximations to the Bernoulli map. Inversely, constructing such one-dimensional maps with finite bits based on other chaotic maps, we can design new types of NFSRs, called extended NFSRs, which can generate new maximal-period sequences. We design such extended NFSRs based on some well-known chaotic maps, which gives a new concept in sequence design. Some properties of maximal-period sequences generated by such NFSRs are investigated and discussed.

This paper studies the anticontrol problem of making a continuous-time system chaotic by using impulsive control. The controller is designed to ensure the controlled orbit be bounded and, meanwhile, the controlled system have positive Lyapunov exponents, which are achieved near a stable limit cycle of the system. One illustrative example is given.

The technique of the digital watermarking is one of the ways to resolve copyright ownership and verify originality of digital contents (e.g. text documents, audio, still images, video, etc.). In this paper, we obtained global robustness and minimal error through using frame based watermarking and including DC and AC coefficients of DCT transform, which extended conventional watermarking method having local robustness and error through using block based and/or AC coefficients only. As a result, the high robustness and quality of our method were proved by several attacks such as lossy image compression, linear filtering, additive noise, scaling, cropping and so on. Watermarks embedded by our method are survived most of JPEG compressions.

The current paper proposes a new method for reducing the computational overhead of fine-to-coarse multi-resolution motion estimation (MRME) on the finest resolution level based on limiting the search region used to consider the motion vectors from the coarsest resolution subband. Half-pel accuracy motion estimation (HPAME) is used in the baseband to achieve an exact motion vector, which has a significant influence on the reconstructed image. However, since this method involves a high computational overhead, the use of selective interpolation is suggested to reduce the computational overhead. The proposed method uses HPAME to estimate exact motion vectors in the baseband, then based on the characteristics of these motion vectors, the motion vectors in the higher frequency subbands are selectively estimated. That is, motion vectors in the higher frequency subbands are only estimated for those blocks with half-pixel accuracy motion vectors in the baseband. Experimental results show that the proposed algorithm can produce better image quality results than the conventional algorithms.

This paper proposes a new blocking artifact reduction algorithm using an adaptive filter based on classifying the block boundary area. Generally, block-based coding, such as JPEG and MPEG, introduces blocking and ringing artifacts to an image, where the blocking artifact consists of grid noise, staircase noise, and corner outliers. In the proposed method, staircase noise and corner outliers are reduced by a 1D low-pass filter. Next, the block boundaries are divided into two classes based on the gradient of the pixel intensity in the boundary region. For each class, an adaptive filter is applied so that the grid noise is reduced in the block boundary regions. Thereafter, for those blocks with an edge component, the ringing artifact is removed by applying an adaptive filter around the edge. Finally, high frequency components are added to those block boundaries where the natural characteristics have been lost due to the adaptive filter. The computer simulation results confirmed a better performance by the proposed method in both the subjective and objective image qualities.

A generic multilevel quality-of-service (QoS) model for distributed multimedia applications is presented. QoS mapping mechanisms are required to translate the QoS parameters among the hierarchical levels. One QoS mapping mechanism based on the spline functions is proposed, hence two splines are compared. One is natural splines and the other is B-splines. QoS measurement experiments were conducted, and it is found that the B-splines give more accurate mapping results than the natural splines once the knots for the splines are selected appropriately.

There are several kinds of coloring of digraphs, such as vertex-coloring and arc-coloring. We call an arc-coloring of a digraph G the first type if it is an assignment of colors to the arc set of G in which no two consecutive arcs have the same color. In some researches, the arc-coloring of first type has been associated with the minimum number of the vertex-coloring called chromatic number. Considering the class of line digraphs, an arc-coloring of a digraph G of the first type is equivalent to the vertex-coloring of its line digraph L(G). In this paper, we study the arc-coloring of the first type and the vertex-coloring of line digraphs. We give the upper bound of the chromatic number of L(G) by the chromatic number of a digraph G which admits loops. It is also shown that there exists quite a small integer k so that the iterated line digraph L^k(G) is 3-vertex-colorable. As a consequence, we derive the chromatic number of de Bruijn and Kautz digraphs.

An n-dimensional crossed cube, CQ_n, is a variation of the hypercube. In this paper, we prove that CQ_n is (n-2)-Hamiltonian and (n-3)-Hamiltonian connected. That is, a ring of length 2ⁿ-f_v can be embedded in a faulty CQ_n with f_v faulty nodes and f_e faulty edges, where f_v+f_en-2 and n3. In other words, we show that the faulty CQ_n is still Hamiltonian with n-2 faults. In addition, we also prove that there exists a Hamiltonian path between any pair of vertices in a faulty CQ_n with n-3 faults. The above results are optimum in the sense that the fault-tolerant Hamiltonicity (fault-tolerant Hamiltonian connectivity respectively) of CQ_n is at most n-2 (n-3 respectively). A recent result has shown that a ring of length 2ⁿ-2f_v can be embedded in a faulty hypercube, if f_v+f_en-1 and n4, with a few additional constraints. Our results, in comparison to the hypercube, show that longer rings can be embedded in CQ_n without additional constraints.

It has been shown that the performances of single-receiver ARQ schemes are largely dependent on the packet-error process, i.e., for dependent packet-error environment, they are under- or over- estimated by analyzing them under the assumption that packet-errors occur at random. While, multi-receiver ARQ's have not been analyzed and evaluated for dependent packet-error process. In this paper, we analyze the throughput efficiency of the fundamental multi-receiver Go-back-N ARQ scheme, which can be implemented very simply, over an unreliable channel modeled by the two-state Markov process. Any receiver erroneously receives a packet with probability inherent to each state. From numerical results, we show that the throughput efficiency of the fundamental multi-receiver Go-Back-N ARQ scheme depends on the number of receivers, round-trip-delay, and the characteristic of the Markov process. Also we show that the throughput efficiency of the fundamental multi-receiver Go-Back-N ARQ scheme for larger decay factor and larger difference between packet error probability at each state is considerably better than that for the random error pattern.

A visual secret sharing scheme (VSSS) is one of secret sharing schemes for images. Droste showed the method for constructing VSSS based on basis matrices whose contrast was high. Koga, Iwamoto, and Yamamoto also proposed the method for constructing a lattice-based VSSS and its polynomial representation. It is known that many good VSSSs are not in the class of lattice-based VSSSs. In this paper, we show the well-defined polynomial representation of a VSSS based on permuting different matrices for black-white images. The necessary and sufficient condition of the existence of a VSSS based on permuting different matrices can be obtained from the proposed polynomial representation. This condition is useful for constructing a good VSSS. We also point out that without additional data, it is possible to achieve member verification by using a VSSS. Using the proposed polynomial representation, the probability of detecting a cheater is analyzed.

Wyner and Ziv considered the rate-distortion function for source coding with side information at the decoder (we call the Wyner-Ziv problem). In this paper we show an information-spectrum approach to the Wyner-Ziv problem for general class of nonstationary and/or nonergodic sources with side information at the decoder, where the distortion measure is arbitrary and may be nonadditive. We show that a general formula for the rate-distortion function of the Wyner-Ziv problem for general sources with the maximum distortion criterion under fixed-length coding by using the information spectrum approach.

A new H.263+ rate control method that has very low encoder-decoder delay, small buffer and low computational complexity for hardware realization is proposed in this paper. This method focuses on producing low encoder-decoder delay in order to solve the lip synchronization problem. Low encoder-decoder delay is achieved by improving target bit rate achievement and reducing processing delay. The target bit rate achievement is improved by allocating an optimum frame encoding bits, and employing a new adaptive threshold of zero vector motion estimation. The processing delay is reduced by simplifying quantization parameter computation, applying a new non-zero coefficient distortion measure and utilizing previous frame information in current frame encoding. The simulation results indicate very large number skipped frames reduction in comparison with the test model TMN8. There were 80 skipped frames less than that of TMN8 within a 380 frame sequence during encoding of a very high movement video sequence. The 27 kbps target bit rate is achieved with insignificant difference for various types of video sequences. The simulation results also show that our method successfully allocates encoding bits, maintains small data at the encoder buffer and avoids buffer from overflow and underflow.

This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to loops and the address computation of array accesses. The information is used in generating hardware loop instructions and parallel instructions provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to make it easy to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance.

A new single resistance controlled quadrature oscillator using two current differencing buffered amplifiers (CDBAs), four resistors and two grounded capacitors is presented. Outputs of two sinusoidal signals with 90phase difference are available in the proposed quadrature oscillator. The oscillation condition and oscillation frequency of the proposed quadrature oscillator are independently controllable through different resistors. The proposed quadrature oscillator employs only grounded capacitors. The use of only grounded capacitors is ideal for integration. Simulation results are included.

In this paper, we present a new approach to the construction of a set of binary sequences with a zero-correlation zone. The set consists of n pairs of binary sequences and the length of each binary sequence is n2^(m+2) for some integers m and n. The Hadamard sequences with length n are used to construct the set. Any sequence in the set has 2^(m+1) subsequences, each of length 2n. The author proves that any two subsequences are orthogonal if they belong to different pairs of binary sequences in the set.

This letter presents a code which corrects single bit errors in any location of the word as well as l-bit burst errors occurred in an important part of the word. The proposed code is designed by product of the parity check matrix of the l-bit burst error correcting codes and the matrix which converts input unequal errors into equal errors. This letter also demonstrates the evaluation of the code, and presents the extended codes with two-level burst error correcting capabilities by interleaving.