A new bipolar linear transconductor for low-voltage low-power signal processing is proposed. The proposed circuit has larger input linear range and smaller power dissipation when compared with the conventional bipolar linear transconductor. The experimental results show that the transconductor with a transconductance of 50 µS has a linearity error of less than 0.02% over an input voltage range of 2.1 V at supply voltages of 3 V. The power dissipation of the transconductor is 3.15 mW.

This paper presents a novel layout approach using dual supply voltage technique. In Placing and Routing (P&R) phase, conventional approaches for dual supply voltages need to separate low supply voltage cells from high voltage ones. Consequently its layout tends to be complex compared with single supply voltage layout. Our layout approach uses cells having two supply voltage rails. Making these cells is difficult in bulk due to increase in area by n-well isolation or in delay by negative body bias caused by sharing n-well. On the other hand, making cells with two supply voltage rails is easy in body-tied PD-SOI owing to trench isolation of each body of transistor. Since our approach for dual supply voltages offers freedom for placement as much as conventional ones for single supply voltage, exsting P&R tools can be used without special operation. Simulation results with MCNC circuits and adders show that our approach reduces power by 23% and 25%, respectively, showing almost the same delay with single supply voltage layout.

In this paper, a novel type of the step-up high frequency transformer linked full-bridge soft-switching phase-shift PWM DC-DC power converter with ZVS and ZCS bridge legs is proposed for small scale fuel cell power generation systems, automotive AC power supplies. A tapped inductor filter with a freewheeling diode is implemented in the proposed soft-switching DC-DC power converter to minimize the circulating current in the high-frequency step-up transformer primary side and high-frequency inverter stage. Using a tapped inductor filter with a freewheeling diode makes possible to reduce the circulating current without any active switches and theirs gate-drive circuits. The operating principle of the proposed DC-DC power converter with each operation mode during a half cycle of the steady state operation is explained. The optimum design of the tapped inductor turns ratio is described on the basis of the circuit simulation results. Developing 1 kW 100 kHz prototype with power MOSFETs and 36 V DC source verifies the practical effectiveness of the proposed soft-switching DC-DC power converter. The actual efficiency of the proposed DC-DC power converter is obtained 94% for the wide load and output voltage variation ranges.

This paper presents a novel ZVS bidirectional 1 kW class DC-DC converter used for a photovoltaic (PV) system. The proposed circuit is based on a boost&buckboost converter, which consists of a boost converter and a buckboost converter. Bidirectional soft switching is realized by using of coupled inductors and auxiliary switches in the circuit. From the analysis of the circuit operation, ZVS conditions of the switches are derived. In the experiment, the maximum efficiency of the proposed converter during forward power flow was 97.1% on output power of 320 W.

This paper presents a novel self-excited ZVS half-bridge converter. This converter including a self-oscillating control circuit is very simply constructed. The converter achieves excellent efficiency, low voltage stress across the switches and low EMI noise by using zero-voltage-switching technique. This converter stores not only magnetic energy in the primary winding of the transformer but also electrostatic energy on the resonant capacitor during the on-periods, so that the converter realizes the miniaturization of the transformer, the reduced conduction losses and the low current stress in the switch. This paper analyzes the behavior of static characteristics by using an extending state-space-averaging method and presents design equations. Based on the analysis, two prototype converters are designed for a 120 W output and a 350 W output. Experimental results are given for two converters and they confirm the validity of the theory. The proposed converters have displayed excellent performance.

This paper presents a multiple-voltage high-level synthesis approach for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by maximization of task mobilities in that the increase of mobilities may raise the possibility of assigning tasks to low-voltage components. The mobility means the ability to schedule the starting time of a task. It is defined as the distance between its as-late-as-possible (ALAP) schedule time and its as-soon-as-possible (ASAP) schedule time. To earn task mobilities, we use loop shrinking, retiming and unfolding techniques. The loop shrinking can first reduce the iteration period bound (IPB) and, then, the others are employed for shortening the iteration period (IP) as much as possible. The minimization of IP results in high task mobilities. Finally, we can assign tasks with high mobilities to low-voltage components and, thus, minimize energy under resource and latency constraints. With considering the overhead of level conversion, our approach can achieve significant power reduction. In the case of the third-order IIR filter, the proposed approach can save up to 40.2% of power consumption.

A new circuit technique based on pass-gate logic with dynamic supply-voltage and clock-frequency control is proposed for a low-power motion-vector detection VLSI processor. Since the pass-gate logic style has potential advantages that have small equivalent stray capacitance and small number of short-circuit paths, its circuit implementation makes it possible to reduce the power dissipation with maintaining high-speed switching capability. In case the calculation result is obtained on the way of calculation steps, additional power saving is also achieved by combining the pass-gate logic circuitry with a mechanism that dynamically scales down the supply voltage and the clock frequency while maintaining the calculation throughput. As a typical example, a sum of absolute differences (SAD) unit in a motion-vector detection VLSI processor is implemented and its efficiency in power saving is demonstrated.

Reconfigurable logic circuitry has special importance because the popularity of Field Programmable Gate Arrays (FPGA) based applications. A reconfigurable logic based on FGMOS transistors, where a single stage can perform binary operations as well as state machines, is presented. The use of the proposed logic allows the integration of several stages into a single chip because their small area requirement, low voltage and low power characteristics.

This paper presents a voltage-mode WTA/MAX circuit that achieves high-speed and multi-chip features. Based on the efficient averaged-value comparison approach, the time and hardware complexities are proportional to O(log N) and O(N) respectively, where N is the number of inputs. In addition, a voltage comparison element (VCE) circuit is proposed to achieve multi-chip function. In the proposed circuit, the averaged-value calculator is built using resistor array that prevents the matching problem of transistor array. The whole circuit was fabricated with the TSMC 0.35 µm signal-poly quadruple-metal CMOS process. With eight input signals, the measurement results show that the proposed circuit resolved input voltages differing by 10 mV in 30 ns, and the multi-chip capability was also verified.

To measure the arc motion in interruption process of low voltage molded case circuit breakers (MCCBs) more precisely, a set of novel 2-D optical fiber system is developed. To improve the spatial resolution of optical fibers, lens with inhomogeneous dielectric is fixed on the top of each fiber. Furthermore, the full hardware control logic facilitates the real-time, synchronous and high-speed processing and breaks through the restricted bus operation frequency range and data stream capacity of microprocessor. The Publisher-Subscribe behavioral design pattern is applied to the software and the loosely coupled relationship between glyph and experimental data is once established, the graphic configuration can be implemented for simulation analysis, and the flexibility and applicability of the whole system are obviously improved. It demonstrates that the system provides a better research technique especially for new generation MCCB with gas driven arc.

The Flex Power FPGA is presented as a novel FPGA model offering the ability to configure the trade-off between power consumption and speed for each logic element by adjusting the threshold voltage. This FPGA model targets the reduction of static power consumption, which has become one of the most important issues in the development of future-generation devices. The present paper describes a preliminary simulation study of the Flex Power FPGA. A method to effectively assign threshold voltages to transistors at a prescribed granularity based on a timing analysis of the mapped circuit is implemented using the VPR simulator, and the static power reduction for 70 nm technologies is estimated using MCNC benchmark circuits. Simulation results show that the average static power can be reduced to as little as 1/30 of that in the corresponding conventional FPGA. This FPGA model is also demonstrated to be effective with future technologies, where the proportion of static power will be greater.

A novel high speed, low voltage BiCMOS tristate buffer is presented and its performance characteristics are investigated by using PSPICE simulation. The results obtained are compared with a general CMOS and a couple of previous BiCMOS tristate buffer circuits which are conventional BiCMOS and complementary BiCMOS tristate buffer circuits. It is shown that the proposed BiCMOS tristate buffer circuit outperforms other previous tristate buffer circuits. At lower supply voltage, the proposed circuit has been shown more advantageous speed over previous circuits and it guarantees speed advantage over previous circuits even supply voltage application is at 1.5 volt. The pass transistor technique with a single MOS transistor driving is used to improve the driving capability. Furthermore, a complementary BiCMOS charge pump technique is used to eliminate the voltage loss due to base-emitter turn on voltage and to enhance the driving capability. With the positive and negative charge pump, it can be realized a high speed at low voltage with full swing operation without performance degradation due to shunt CMOS circuit as same as previous complementary BiCMOS tristate buffer circuit.

A new CMOS positive charge pump (NCP-1) is proposed and compared with the conventional pump in this paper. The comparison indicates that this NCP-1 scheme delivers 1.6 times larger output current into the load with roughly 10% area penalty than the conventional pump. To alleviate the area overhead of NCP-1, another new NCP-2 is proposed, where its current drivability is slightly lower than NCP-1 by as small as 5% but it achieves much smaller layout penalty as small as 2-3% compared with the conventional pump. The effectiveness of NCP-1 is verified experimentally in this paper by using 0.35-µm n-well process technology. These NCP-1 and NCP-2 are useful to DRAMs and NOR-type flash memories with sub-1-V VDD, where their large-output-current nature is favorable.

The threshold voltage mismatch of FD (Fully depleted) SOI (Silicon on insulator) devices have been studied. Floating body MOSFETs operating at high drain voltage show a large mismatch in the threshold voltage compared with body-tied MOSFETs. Those experimental data under different drain voltages indicate that both floating body effect and DIBL (Drain induced barrier lowering) are involved in the threshold voltage mismatch of floating body MOSFETs.

A low supply voltage CMOS variable-gain low noise amplifier (LNA) is presented in this paper. A folded cascode structure is used to reduce the supply voltage to only 1 V. The conversion gain of the LNA can be controlled by the bias voltage of the connon-gate transistor. When the input signal is weak, the circuit works at high-gain mode to improve the sensitivity. Otherwise, when the input signal is strong, the circuit works at low-gain mode to increase the linearity.

A CMOS voltage-to-current converter in weak inversion is presented in this Letter. It can operate for low supply voltage and its power consumption is also low. As the input voltage varies from -0.15 V to 0.15 V, the measured maximum linearity error for the proposed voltage-to-current converter, is about 3.35%. Its power consumption is only 26 µW under the supply voltage of 2 V. The proposed voltage-to-current converter has been fabricated in a 0.5 µm N-well CMOS 2P2M process. The proposed circuit is expected to be useful in analog signal processing applications.

A Switched-Opamp is a device in SC circuits for replacing switches with Opamps which operate like a switch. This technique can be acheived in very low voltage operation. In this paper, we present a design for a Switched-Opamp that can operate at a low supply voltage during the ON-phase and can maintain a high output impedance during the OFF-phase.

This paper presents a novel class of sigma-delta modulator topologies for low-voltage, high-speed, and high-resolution applications with low oversampling ratios (OSRs). The main specifications of these architectures are the reduced analog circuit requirements, large out-of-band gain in the noise transfer function (NTF) without any stability concerns to achieve high signal to noise ratio (SNR) with a low OSR, and unity-gain signal transfer function (STF) to reduce the harmonic distortions resulted from the analog circuit imperfections. To demonstrate the efficiency of the proposed modulator architectures a prototype with HSPICE is implemented. A low-power two-stage class A/AB OTA with modified common mode feedback (CMFB) circuit in the first stage is used to implement the fourth order modulator. Simulation results with OSR of 16 give signal to noise plus distortion ratio (SNDR) and dynamic range (DR) of 90-dB and 92.5-dB including the circuit noise in the 1.25-MHz signal bandwidth, respectively. The circuit is implemented in a 0.13-µm standard CMOS technology. It dissipates about 40-mW from a single 1.2-V power supply voltage.

In this work, a simple method for extracting MOSFET threshold voltage, effective channel length and channel mobility by using S-parameter measurement is presented. In the new method, the dependence between the channel conductivity and applied gate voltage of the MOSFET device is cleverly utilized to extract the threshold voltage, while biasing the drain node of the device at zero voltage during measurement. Moreover, the effective channel length and channel mobility can also be obtained with the same measurement. Furthermore, all the physical parameters can be extracted directly on the modeling devices without relying on specifically designed test devices. Most important of all, only one S-parameter measurement is required for each device under test (DUT), making the proposed extraction method promising for automatic measurement applications.

This paper proposes a sensing and a precharge circuit schemes suitable for low-voltage and high-speed DRAM design. The proposed offset-compensated direct sensing scheme improves refresh characteristics as well as speed performance. To minimize the number of control switches for the offset compensation, only the output branches of differential amplifiers are implemented in each bit-line pair with a semi-global bias branch, which also reduces 50-percent of bias current. The addition of the direct sensing feature to the offset-compensated pre-sensing dramatically increases the differential current output. For the fast bit-line equalization, a charge-recycled precharge scheme is proposed to reuse VPP discharging current for the generation of a boosted bias without additional charge pumping. The two circuit schemes were verified by the implementation of a 256 Mb SDRAM with a 0.1 µm dual-doped poly-silicon technology.