A new contention-free Domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional Domino circuits for LVTs are demonstrated using HSPICE(R) simulations and a 0.25 µm CMOS technology with a supply voltage of 2.5 V. The impacts of the new technique on dynamic and leakage powers and area were evaluated. At a 3% area increase, and keeping the noise margins constant, the new CF-DOMINO achieves 20% less delay than conventional DOMINO as the threshold voltage scales from 450 mV down to 200 mV. It also achieved 13% less dynamic power and 5% less leakage at that threshold voltage.

Recent advances make it possible to mitigate a number of drawbacks of conventional phase locked loops. These advances permit the design of phase tracking system with much improved characteristics that are sought after in modern communication system applications. A new phase tracking system is outlined which reduces the effects of VCO phase noise to an insignificant level. This fact permits extremely narrow bandwidth phase tracking systems to be realized, even when a VCO with poor phase noise characteristics is employed. The improvement in performance over conventional phase locked loops is analyzed. The new phase tracking system also has other benefits such as precise centre frequency and elimination of peaking in the transfer function. To implement the phase tracking system requires a frequency measurement. We outline a new highly integrated frequency measurement method suitable for narrow bandwidth applications. Experimental results from a prototype confirms theoretical results.

A charge pump circuit suitable for positive high voltage generators at sub-1.5 V range is presented. The proposed heap-pump circuit provides a high voltage generator having not only high pumping efficiency by eliminating threshold voltage drop but also simplest single phase clock scheme.

We report our studies on electrical current pulse perturbation of superconducting YBa2Cu3O7-x (YBCO) epitaxial thin films. When a current pulse is applied to a YBCO microbridge, a voltage develops across it that depends on the amplitude of the input current pulse. For a total current (input current pulse plus the dc bias) that is lower than the critical current Ic, an inductive voltage response is observed. When the total current exceeds Ic, a resistive response is generated and is observed after a certain delay time td. The origin of the resistive response was analyzed using the Geier and Schon model, which is based on the time-dependent Ginzburg-Landau equation. Our experimental samples consisted of 200-nm-thick epitaxial YBCO films, patterned into coplanar-strip (CPS) transmission lines, containing either two-microbridge or single-microbridge test structures. For the two-microbridge samples, a train of 100-fs-duration optical pulses was used to excite the larger microbridge and generate 2-ps-duration electrical pulses, which were then applied to perturb the smaller microbridge, which was independently biased in the superconducting state. In this case, an electro-optic sampling system was used to measure the YBCO kinetic-inductive voltage responses with the picosecond time resolution. For the single-microbridge structures, an electronic pulse generator was employed to supply the input current pulse, and a 14-GHz sampling oscilloscope was used to monitor the microbridge responses. The latter signals were in very good agreement with the model of Geier and Schon, assuming that the quasiparticle dynamics process that resulted from the nanosecond-wide current excitation was bolometric and followed the phonon escape time τes.

We present measurements of kilohertz and megahertz sine waves synthesized using a Josephson arbitrary waveform synthesizer. A 4.8 kHz sine wave synthesized using an ac-coupled bias technique is shown to have a stable 121 mV peak voltage and harmonic distortion 101 dB below the fundamental (-101 dBc (carrier)). We also present results of our first phase-noise measurement. A 5.0 MHz sine wave was found to have distortion 33 dB lower than the same signal synthesized using a semiconductor digital code generator. The white-noise floor of the Josephson synthesized signal is -132 dBc/Hz and is limited by the noise floor of the preamplifier.

The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (Vdd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.

A building block for widening an input range under low power-supply voltages is proposed and the block is used in a popular linearization technique for voltage-to-current converters. The block employs two MOSFETs each of which actively works when and only when the other is in cutoff region. Accurate level shift circuits for the control of the MOSFETs enable such exclusive operation. Simulation results show that the complementary MOSFETs perform as an equivalent MOSFET without any cutoff region. It is also confirmed that the novel linear voltage-to-current converter is effective for not only a wide input range but also low-power consumption.

An LSI has been fabricated and measured to demonstrate feasibility of VDD-hopping scheme in an embedded system level by executing MPEG4 CODEC. In the VDD-hopping, supply voltage of a processor is dynamically controlled by a hardware-software cooperative mechanism depending on workload of the processor. When the workload is about a half, the VDD-hopping is shown to reduce power to less than a quarter compared to the conventional fixed-VDD scheme. The power saving is achieved without degrading real-time features of MPEG4 CODEC.

With increased size and issue-width, instruction issue queue becomes one of the most energy consuming units in today's superscalar microprocessors. This paper presents a novel architectural technique to reduce energy dissipation of adaptive issue queue, whose functionality is dynamically adjusted at runtime to match the changing computational demands of instruction stream. In contrast to existing schemes, the technique exploits a new freedom in queue design, namely the voltage per access. Since loading capacitance operated in the adaptive queue varies in time, the clock cycle budget becomes inefficiently exploited. We propose to trade-off the unused cycle time with supply voltage, lowering the voltage level when the queue functionality is reduced and increasing it with the activation of resources in the queue. Experiments show that the approach can save up to 39% of the issue queue energy without large performance and area overhead.

A 1-V 2-GHz receiver that exhibits an image rejection of 49 dB is described. It consists of a low-noise amplifier, a quadrature mixer and on-chip polyphase filters, and was fabricated by 0.2-µm fully depleted CMOS/SIMOX technology. The quadrature mixer employs an LC-tuned folded structure with a common RF input for I and Q channels. This enables 1-V operation, suppresses phase errors in LO signals, and improves the image-rejection performance by about 15-dB compared to a conventional quadrature architecture. The current source of the single-to-balance converter at the mixer input consists of a transistor and an LC tank in a cascode configuration. This enhances its output impedance and improves its common-mode-rejection ratio (CMRR) and the IIP2 characteristics of the receiver. The chip consumes 12 mW with 1-V power supply. The receiver provides an NF of 10 dB with an IIP3 of -15.8 dBm and IIP2 of 12.3 dBm.

This paper describes 2.4-GHz-band front-end building circuits--a down conversion mixer (DCM), a dual-modulus divide-by-4/5 prescaler, a transmit/receive antenna switch (SW), a power amplifier (PA), and a low noise amplifier (LNA). They are fabricated using a standard bulk 0.18 µm CMOS process with a lower current consumption than bipolar circuits, and can operate at the low supply voltage of 1.8 V. Meshed-shielded pads are adopted for lower receiver circuit noise. Pads shielded by metals become cracked when they are bounded, therefore silicided active areas are used as shields instead of metals to avoid these cracks. The meshed shields achieve lower parasitic pad capacitors without parasitic resistors, and also act as dummy active areas. The proposed DCM has a high IP3 characteristic. The DCM has a cascode FET configuration and LO power is injected into the lower FET. By keeping the drain-source voltage of the upper transistor large, the nonlinearity of the drain-source transconductance is reduced and a low distortion DCM is realized. It achieves a higher input referred IP3 with a higher conversion gain for almost the same current consumption of a conventional single-balanced mixer. The output referred IP3 is higher 5.0 dB than the single-balanced mixer. The proposed dual-modulus prescaler employs a fully-differential technique to achieve stable operation. In order to avoid errors, the fully-differential circuit gives the logic voltage swing margins. In addition, the differential technique also reduces the noise effect from the supply voltage line because of the common-mode signal rejection. The maximum operating frequency is 3.0 GHz, and the one flip-flop power consumption normalized by the maximum operating frequency is 180 µW/GHz.

To overcome the problems of the modified Dickson pump like NCP-2, another pump (CCTS-1) where simple voltage doublers are cascaded in series and each of them has cross-coupled configuration is studied in this letter for possible use in low-voltage EEPROMs and DRAMs. Though this concept of cascading doublers has been previously proposed, it is firstly addressed in this letter that CCTS-1 has lower gate-oxide stress, improved voltage pumping gain, and better power efficiency than NCP-2 so that CCTS-1 can be more suitable for multi-stage pump in particular at low VCC. In addition, CCTS-2 is proposed to overcome the degraded body-effect of CCTS-1 without using boosted clocks when the stage number is large.

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage (VOL) to be equal to the reference voltage (VOL.ref) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1 Gb/s. The worst-case variations of VOL.ref and VOL of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of 20 to 90 and a supply voltage range of 2.25 V to 2.75 V, while the worst-case variation of VOL of the conventional output driver was measured to be 24% within the same ranges of temperature and supply voltage.

The concept of a "standardized brain" is familiar in modern functional neuro-imaging techniques including PET and fMRI, but it has never been adopted for optical imaging studies that deal with a regional cortical area rather than the whole brain. In this paper, we propose a "standardized barrel cortex" for rodents, and present a method for mapping optically detected neural activity onto the standard cortex. The standard cortex is defined as a set of simple cortical columns, which are modeled on the cytoarchitectonic patterns of cell aggregates in cortical layer IV of the barrel cortex. Referring to its underlying anatomical structure, the method warps the surface image of individual cortices to fit the standard cortex. The cortex is warped using a two-dimensional free-form deformation technique with direct manipulation. Since optical imaging provides a map of neural activity on the cortical surface, the warping consequently remaps it on the standard cortex. Data presented in this paper show that somatosensory evoked neural activity is successfully represented on the standardized cortex, suggesting that the combination of optical imaging with our method is a promising approach for investigating the functional architecture of the cortex.

A priming effect is studied for a three-electrode, surface-discharge AC-PDP, which has stripe barrier ribs of 0.22 mm pitch. It was found that by keeping the interval between the reset and address pulses within 24 µs, the data pulse voltage can be reduced while the data pulse width can be narrowed due to the priming effect. By adopting the primed addressing technique to the PDP, the data pulse voltage was reduced to 20 V when the data and scan pulse widths were 1 µs. Alternatively, the data pulse width could be narrowed to 0.33 µs when the data pulse voltage was 56 V. 69% of the TV field time could be assigned for the display periods with 12 sub-fields, assuring high luminance display.

A system level approach for a memory power reduction is proposed in this paper. The basic idea is allocating frequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory. Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation. Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation including static power dissipation caused by leakage current. A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well. Our experiments with some benchmark programs demonstrate significant energy reductions up to 80% over a program memory which does not employ our approach.

We have developed InGaP-channel field effect transistors (FETs) with high breakdown voltages that can be fabricated by using conventional GaAs FET fabrication processes. The buffer and barrier layers were also optimized for the realization of high-voltage operation. The InGaP-channel FET has an extremely high on-state drain-to-source breakdown voltage of over 40 V, and a gate-to-drain breakdown voltage of 55 V. This enabled high-voltage large-signal operation at 40 V. The third-order intermodulation distortion of the InGaP channel FETs was 10-20 dB lower than that of an equivalent GaAs-channel FET, due to the high operating voltage.

We report here on the electrical and structural characteristics of InGaP/GaInAsN DHBTs with up to a 50 mV reduction in turn-on voltage relative to standard InGaP/GaAs HBTs. High p-type doping levels ( 3 1019 cm-3) and dc current gain (βmax up to 100) are achieved in GaInAsN base layer structures ranging in base sheet resistance between 250 and 750 Ω/. The separate effects of a base-emitter conduction band spike and base layer energy-gap on turn-on voltage are ascertained by comparing the collector current characteristics of several different GaAs-based bipolar transistors. Photoluminescence measurements are made on the InGaP/GaInAsN DHBTs to confirm the base layer energy gap, and double crystal x-ray diffraction spectrums are used to assess strain levels in the GaInAsN base layer.

This paper presents improved versions of three-stage positive-output and two-stage negative-output Dickson charge-pump circuits which are intended to replace switching regulators in video-product CCD driver applications (where 12 V and -6.5 V are needed), and are designed and fabricated in a custom CMOS process. From a power supply Vdd of 4.0 to 5.5 V, the positive charge pump generates a positive output voltage of greater than 3.9Vdd, while the negative charge pump generates a negative voltage of greater than -1.9Vdd, both with efficiencies of greater than 94% at 2 mA output currents.

This paper introduces a switched-voltage delay cell with differential inputs. It can be used as a building block for a range of analogue functions such as voltage-to-frenquency converter, A/D converter, etc. Applications incorporating the delay cell are presented. The performances are verified by simulations on PSpice.