A GaAs power amplifier IC has been developed for 1. 9-GHz digital mobile communication applications, such as the handsets of the Japanese personal handy phone system (PHS), which was assembled into a very small 0. 012-cc surface mount plastic package. This power amplifier using refractory WNx/W self-aligned gate MESFETs with p-pocket layers can operate with high efficiency and low distortion with a single 3-V supply. A very low dissipated current of 119 mA was obtained with an output power of 21. 1 dBm and a low 600-kHz adjacent channel leakage power (ACP) of -63 dBc for π/4-shifted quadrature phase shift keying (QPSK) modulated input.

This paper describes the evaluation of the Voltage Down Converter (VDC) with low ratio of consuming current to load current in DC/AC operation mode. The stability, response and power consumption are investigated. First, for the stability and response, the VDC can operate in the condition that the bounce of the down voltage (dVDL) is no more than 10% of the setting voltage and the maximum load operation frequency (fmax) is 100 MHz at the average load current 70 mA (the maximum load current 140 mA). Secondly, for the power consumption, by using this VDC technology, the value of IC/IL can be suppressed to 5.1E-4 (IC: total consuming current in VDC, IL: average load current) in the condition that dVDL is no more than 10% of the setting voltage and fmax is 10 MHz at the average load current 70 mA. Thus, it is made clear that the VDC can realize high stability, good response and low power consumption at the same time. This technology is suitable for high performance ULSIs which require large load current and low-power consumption.

A GaAs power MESFET amplifier with a low-distortion, 10-dB gain-variable attenuator has been developed for 1. 9-GHz Japanese personal handy phone system (PHS). Independently of its gain, a very low 600-kHz adjacent channel leakage power (ACP) with sufficient output power was attained. In single low 2. 4-V supply operation, an output power of 21. 1 dBm, a low dissipated current of 157 mA and a high power-added efficiency (PAE) of 37. 2% were obtained with an ACP of -55 dBc.

This paper describes design approach and power performance of a single 1. 5 V operation two-stage power amplifier MMIC for 2. 4 GHz wireless local area network applications. The MMIC with 0. 760. 96 mm2 area includes SrTiO3 (STO) capacitors with a high capacitance density of 8. 0 fF/µm2 and double-doped AlGaAs/InGaAs/AlGaAs heterojunction FETs with a shallow threshold voltage of -0. 24 V. Utilizing a series STO capacitor and a shunt inductor as an output matching circuit, the total chip size was reduced by 40% as compared with an MMIC utilizing SiNx capacitors. Under single 1.5 V operation, the developed MMIC delivered an output power of 110 mW (20.4 dBm) and a power-added efficiency (PAE) of 36.7% with an associated gain of 20.0 dB at 2.4 GHz. Even operated at a drain bias voltage of 0.8 V, the MMIC exhibited a high PAE of 31.0%.

This letter describes new active building blocks defined as the generalized voltage conveyor (GVC) and the generalized current conveyor (GCC). A very simple practical realization of the GVC using the second generation current conveyors (CCII) is given. The special cases of the first generation voltage conveyor (VCI) and the second generation voltage conveyor (VCII) are also considered. A practical realization of the GCC using the CCII is also given. Applications of the voltage and current conveyors in oscillators are considered.

Ferroelectric non-volatile memory (FeRAM) has been inspiring interests since bismuth layer perovskite material family was found to provide "Fatigue Free" endurance, superior retention and imprint characteristics. In this paper, we will provide new circuits technology for FeRAM developed to implement high speed operation, low voltage operation and low power consumption. Performance of LSI embedded with FeRAM for contactless IC card is also provided to demonstrate the feasibility of the circuit technology.

The electromagnetic interference (EMI) induced by steady arc has been demonstrated to be dependent on arc voltage fluctuation when the arc transfers from the metallic phase to the gaseous phase. In order to give the physical understanding of this arc voltage fluctuation and EMI, several typical materials, such as Ag, Cu and Zr, were tested and their arc behavior was determined and compared. The experimental results indicated that the arc behavior, in particular the arc voltage fluctuation in the moment that metallic phase transfers to the gaseous phase was different for different materials. Based on the test results and former investigations, a plausible mechanism is proposed for understanding these phenomena.

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (1. 5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 µW, it has a sufficient input range, whereas conventional Wang's OTA needs 703 µW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.

A technique for realization of low-voltage OTAs is presented in this letter. A very low-voltage differential-output OTA is realized by employing a new common-mode amplifier in the common-mode feedback circuit. The results of PSpice simulations are shown. The proposed OTA can operate at a 0. 9 V supply voltage.

In this paper, a threshold voltage (VT) cancellation circuit for neuron-MOS (νMOS) analog circuits is described. By connecting the output terminal of this circuit with one of the input terminals of the νMOS transistor, cancellation ofVT is realized. The circuit has advantages of ground-referenced output and is insensitive to the fluctuation of bias and supply voltages. Second-order effects, such as the channel length modulation effect, the mobility reduction effect and device mismatch of the proposed circuit are analyzed in detail. Low-power and high-swing νMOS cascode current mirror is presented as an application. Performance of the proposed circuits is confirmed by HSPICE simulation with MOSIS 2. 0 µ p-well double-poly and double-metal CMOS device parameters.

Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.

The proposed high-power-factor converter is constructed with a flyback converter, and locates the energy-storage capacitor on the secondary side of the transformer. A high power-factor can be obtained without needing to detect any current, and the ZVS operation can be achieved without auxiliary switches. To make the best use of these advantages in the converter, ZVS operations and power-factor characteristics in the converter were analyzed. From the analytical results, the effective control method for achieving ZVS was examined. Using a bread-board circuit controlled by this method, a power-factor of 0.99 and a conversion efficiency of 88% were measured.

A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.

The cell structure of surface discharge ACPDPs with a long gap between the sustaining electrodes achieves high luminous efficiency. However, the long gap cell structure causes high firing voltage and thus makes driving more difficult than with the conventional gap cell structure. The rise in firing voltage in the long gap cell structure could not be explained by Paschen's scaling law. We derived a new governing equation for firing voltage, involving the influence of a non-uniform electric field, to investigate this deviation from Paschen's law. From the calculated results we found that changing the gap length corresponds to the change in the degree of distortion of the electric field between the sustaining electrodes.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.

Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2µm fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a nonuniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.

A high performance, high-swing CMOS cascode current mirror operating with 1V power supply voltage and using standard CMOS technology is presented. The present circuit employs PMOS source-coupled pair as voltage level shifter to reduce the power supply voltage requirement. The additional advantages of the use of the source-coupled pair are the improved output resistance and the automatic adaptive biasing, thereby enabling the high-swing of output terminal, when used in the cascode configuration. An analytical discussion of the circuit is carried out and the results are confirmed by SPICE simulation. SPICE simulation results show that the input voltage requirement is 370mV and the minimum output voltage requirement is 273mV at the maximum input current of 40µA, whose requirements decrease with decreasing input currens. The output resistance is shown to be greater than 4MΩ at the maximum output current of 40µA, which increases with decreasing output currents. The -3dB bandwidth is shown to be greater than 400MHz and the total harmonic distortion better than -54.34dB at 100kHz at the maximum peak-to-peak input current swing of 40µA. The present circuit will be useful for the low voltage, low power, high-performance mixed analog/digital signal processing.

A small-sized three-stage GaAs power module has been developed for portable digital radios using M-16QAM modulation. This module has exhibited typical P1dB of 10 W with PAE of 48% and a power gain of 35 dB at a low supply voltage of 6.5 V in 1.453-1.477 GHz band. The volume of the module is only 1.5 cc, which is one of the smallest value in 10 W class modules ever reported. In order to realize the reduced size and the high power performances simultaneously, the module has employed new power divider/combiner circuits with significant features of the reduced occupation area, the improved isolation properties and the function of second-harmonic control.