The square-law characteristics of MOSFET in the saturation region have a parameter of threshold voltage VT. However, it introduces some complexities to the circuit design since it depends on kinds of MOS technology and cannot be controlled easily. In this paper, we show an equivalent MOSFET cell which has VT-programming capability and some application instances based on it. The simulation is carried out using CMOS 0.8 µm n-well technology and the results have shown the feasibility of the proposed structure.

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOSFET (FG-MOSFET) is proposed. First, the grounded VCLVR realization is discussed. The proposed circuit consists of only an ordinary MOSFET and an FG-MOSFET. The advantages of the proposed VCLVR are low-power and wide-input range and also the power consumption of the proposed VCLVR is the same as an ordinary passive resistor. The performance of the proposed circuits are confirmed by HSPICE simulations with a standard 0.6 µm CMOS process parameters. Simulations of the proposed VCLVR demonstrate a resistance value of 40 kΩ to 338 kΩ and an input range of 4.34 V within THD of less than 1.1%. Next, we proposed a new floating node linear variable resistor using the proposed VCLVR. The performance of the circuit is also evaluated through HSPICE.

A mapping circuit in order to have a wider input dynamic range is proposed. MOSFET's connecting between power supply lines are employed to construct the mapping circuit. SPICE simulation is shown to evaluate the proposed circuits. With the proposed mapping circuit, two-MOSFET subtractor has a rail-to-rail input voltage. As an application, an OTA consisting of subtractors is realized by employing the proposed mapping circuits to have a rail-to-rail input voltage range.

A simple and practical methodology to make microwave voltage-controlled oscillators (VCOs) very linear is presented. Incorporating a very short microstrip line ( λg/4) for varactor's bias feed, the C-V curve was shifted by a constant -Δ C and performed a capacitance tailored nearly proportional to VCONT-2. This modification featured very linear VCO implementation at no expense of housing and phase noise performance. Ka- and Ku-band VCOs fabricated with this new technique exhibited a constant tuning sensitivity in a wide control voltage range (2-10 V). The phase noise level at 100 kHz offset was as low as -107 dBc/Hz for a 13 GHz-band VCO and better than -85 dBc/Hz for a 38 GHz-band VCO, due to combination of capacitor-coupled high-Q resonator and multiplier. This technology is very effective for quasi-millimeter-wave and millimeter-wave FM/FSK modulation and FMCW radar applications.

This paper describes an effective model which reproduces the dependence on the source/drain (S/D) process of the reverse short channel effect (RSCE) of the MOSFET threshold voltage (Vth). It is useful for local modeling which is effective within the limited process conditions. The proposed model is based on the physics where the key factor of RSCE is the dopant pile-up in the Si/SiO2 interface. The purpose of the model is for TCAD to be put to actual use as a quick solution tool. The calculation cost is much lower than a pair diffusion model, because the model is implemented in a conventional process simulator that solves one equation for each impurity. The capability of the simplified model is investigated for the dependence of various process conditions on the RSCE. Using our model, we also report the application of both the actual n-channel and p-channel MOSFETs.

We developed the new electron gun, which can emit about twice electron in comparison with the conventional gun and could achieve the screen brightness of over 300 cd/m2 even if the ordinal driving circuit is applied. We tried two methods to improve the drive characteristics, and we chose to lower the cathode cut-off voltage. To maintain the resolution, we optimized the triode. And we used the tungsten-coated oxide cathode to guarantee the long life.

A method to characterise the wall voltage distribution in a three-electrode AC PDP cell is discussed. The method makes use of a firing voltage loop in a two-dimensional voltage plane. From this "fingerprint," data on the relative wall voltages as well as on the non-uniformity of the wall voltages can be inferred. The properties of the loop are explained using a simple numerical model based on field line tracing. The fingerprint method is applied to analyse ramp waveforms on the scan and data electrode of a surface discharge PDP. Many features of the measurements can be understood in terms of uniform wall voltage distributions on the dielectrics covering the electrodes. A more detailed analysis, however, shows that considerable wall voltage non-uniformities can exist, which play an important role in the firing behaviour of the cell.

A low-voltage silicon-on-insulator (SOI) voltage-reference circuit has been developed. It is based on threshold-voltage-summation architecture and the output is not affected by the input offset of the feedback amplifier. Thus, the output dispersion is considerably reduced. An undoped MOSFET is used as a depletion-mode transistor because of its small threshold voltage. The temperature dependence of normal and undoped MOSFETs in fully depleted CMOS/SOI technology is studied for designing a temperature-insensitive voltage-reference circuit. A prototype circuit, fabricated on a fully depleted CMOS/SIMOX process, has a measured reference voltage of 530 16.8 mV (3σ), and can operate at a supply voltage as low as 0.6 V. The measured temperature coefficient is 0.02 0.06 mV/ (3σ).

Problems concerning a phase-locked loop (PLL) fabricated by a deep-sub-micron process were investigated, and a high-speed self-calibration technique for tuning a voltage-controlled oscillator (VCO) frequency range automatically was developed. The self-calibration technique can measure VCO frequency in short time by comparing intervals between a PLL reference and a VCO output. Furthermore, a loop-filter bypassing method was also used to change the calibration frequency in short time. At 0.7 V and 200 MHz, the prototype PLL has a calibration time of 1.4 µs and a total settling time of 10 µs, which are adequate for microprocessor applications. Moreover, the PLL has a cycle-to-cycle jitter of 142 ps and a power consumption of 470 µW.

This paper describes low-power and low-voltage analog circuit techniques applicable to deep sub-micron LSIs in baseband and RF signal processing. The trends indicate that reductions in the supply voltage are inevitable, that power dissipation will not become sufficiently low, and that performance will improve continuously. Some circuit techniques currently being used to achieve these goals are reviewed. Next, three trial approaches are introduced. The first of these is a 1 V operational video-speed CMOS sample-and-hold IC. The second is a 1 V operational high-frequency CMOS VCO circuit. Finally, a step-down DC-DC converter IC with a 1 V output and a greater than 80% power efficiency is introduced. These approaches prove that the low-power and low-voltage operation of analog circuits can be realized without sacrificing performance.

We have developed a 6-bit flash ADC powered from a single 1.8 V supply, using a bipolar based BiCMOS process. Measurements revealed that it operates up to 340 Msps at 1.26 V power supply consuming 36 mW. The conversion rate per power performance index of 9.4 Msps/mW is the highest in the fast 6-bit ADCs reported to date. To operate at this low supply voltage, a new encoder scheme, together with the unique layout, was devised which also substantially improved sparkle error rate. The encoder circuits was synthesized in a new logic topology that we named "folding logic. " This new logic topology is not only suitable for low-voltage operation but also intrinsically fast.

The surface film of a slip ring is important for the sliding contact phenomenon. The surface film is affected by atmospheric temperature, humidity and air pressure. The main objective of our study is to examine the effect of oxygen gas on the sliding contact phenomenon. In the present experiment, we examined the contact voltage drop for continuous sliding when the atmosphere is changed from low pressure to atmospheric pressure by introducing oxygen (O2 20%+N2 80%) or nitrogen gas. As a result, the contact voltage drop increases rapidly with increasing gas pressure, and its fluctuation also becomes large. These phenomena are observed in both cases of oxygen (O2 20%+N2 80%) and nitrogen introduction. The results clearly show that the sudden increase of contact voltage drop is affected by factors other than the oxide film. Actually, the oxide film is not formed in the nitrogen atmosphere. Furthermore, the frictional coefficient of carbon and copper ring is changed at ambient atmosphere. It is inferred from these data that the contact voltage drop may be affected by the frictional coefficient. When the gas pressure decreases again, the contact voltage drop does not suffer from the effect of ambient gas. Therefore, only the resistance of the oxide film appears to affect contact voltage drop. In this paper, the effect of sliding contact phenomenon on the contact voltage drop by gas adsorption and film generation was examined.

The conventional average model for a pulse width modulator employed in a voltage-mode-controlled pulse width modulated converter tends to be numerically unstable when the on-time duty ratio becomes sufficiently small. This paper presents a new average model for a voltage-mode control modulator that is not susceptible to such numerical problems. The validity of the proposed model is confirmed with cycle-by-cycle simulations using an exact discrete-time model.

For wireless communication, a low-voltage monolithic LC-tank CMOS voltage-controlled-oscillator (VCO) is developed with 0.2-µm fully-depleted silicon-on-insulator (SOI) CMOS process technology. The VCO features a double-tuning technique to achieve a wide tuning range with lateral p-n junction varactors. The VCO has the following features at the supply voltage of 1.5 V: (1) Output frequency range from 1.07 GHz to 1.36 GHz, (2) Third-harmonic below -37 dBc, and (3) Phase noise of -120 dBc/Hz at 1 MHz offset frequency.

With the progress of integration of circuits and PCBs (Printed Circuit Boards), novel techniques have been required for verification of signal integrity. Noise analysis of the power/ground planes is one of the most important issues. This paper describes a high-speed simulator for PCBs which contain the interconnects with nonlinear terminations. This simulator is based on the environmental tool ASSIST (Assistant System for Simulation Study) constructed for development of the circuit simulators, and is combined with PRIMA (Passive Reduced-Order Interconnect Macromodeling Algorithm). In this simulator, an efficient implementation of PRIMA is considered with using a voltage-controlled current source (VCCS) model. Finally, this simulator is applied to the analysis of power/ground planes of the simple PCBs, and the validity is verified.

This paper proposes design of new linear bipolar OTAs using hyperbolic circuits with an intermediate voltage terminal. Four types of the OTAs are presented; two OTAs contain a hyperbolic sine circuit and the other two OTAs employ a hyperbolic cosine circuit. The linear input voltage range of the proposed OTAs is wider than that of the well-known conventional OTA, multi-TANH doublet, while each proposed OTA has advantages, such as low power dissipation, high-frequency characteristics and so on. The results of SPICE simulation show that satisfactory characteristics are obtained.

Self-ordered mesoporous silicate films from organic-inorganic compound materials are successfully fabricated into the surface photo voltage (SPV) type gas sensor device as a gas adsorption insulator layer. These kinds of gas sensors device exhibit NO gas sensing property dependent on their mesoporous film structure. We are succeeded in indication about a possibility of mesoporous silicate film for the SPV type gas sensor application.

In this paper, a time-to-digital converter in which the digital output is obtained without delay time is proposed. The circuit consists of a time-to-voltage converter, voltage-to-frequency converter, and counter. In the time-to-voltage converter, a capacitor is charged with a constant current during the input time interval. The change in the capacitor voltage is proportional to the input time and the capacitor voltage can be converted into a pulse signal with the voltage-to-frequency converter. The frequency of the pulse signal is directly proportional to the peak capacitor voltage and the pulse signals are counted to obtain the digital output. In the proposed circuit, the input time interval can be easily controlled and the resolution of the digital output can be improved by controlling the passive devices such as the capacitor and resistor.

We have developed 100 nm node CMOS technology, consisting of a 65 nm gate length and a 1.6 nm gate oxide thickness. The major transistor design issue is how to maintain drive current at supply voltage of only 1.0 V, while suppressing standby leakage current to a practical level for system-on-a-chip applications. In order to obtain thinner electrical equivalent oxide thickness with well-suppressed gate leakage current, we have adopted radical nitridation and poly-SiGe. We have also utilized low-energy ion-implantation, low-temperature CVD, and spike RTA technology to overcome the short channel effect. With supply voltage of 1.0 V, our generic transistor shows the drive current of 520/196 µA/µm with the off current of 0.5 nA/µm. We also designed high-speed (Ioff=5 nA/µm), ultrahigh-speed (Ioff=30 nA/µm) transistors, and low-standby power (Ioff=5 pA/µm), all of which can be deployed on the same chip.

A new contention-free Domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional Domino circuits for LVTs are demonstrated using HSPICE(R) simulations and a 0.25 µm CMOS technology with a supply voltage of 2.5 V. The impacts of the new technique on dynamic and leakage powers and area were evaluated. At a 3% area increase, and keeping the noise margins constant, the new CF-DOMINO achieves 20% less delay than conventional DOMINO as the threshold voltage scales from 450 mV down to 200 mV. It also achieved 13% less dynamic power and 5% less leakage at that threshold voltage.