A buried gate AlGaAs/InGaAs heterojunction FET (HJFET) with gate breakdown voltage of 30 V was examined for high drain bias (higher than 10 V) operation. High breakdown voltage was realized due to the optimization of the narrow recess depth. A 1.4 mm HJFET has exhibited an output power of 30.2 dBm (1050 mW) with 50% power added efficiency (PAE) and 12.1 dB linear gain at 12 GHz with a 13 V drain bias. An internal matching circuit for a 16.8 mm HJFET was designed using a large-signal load impedance determined from load-pull measurement. The 16.8 mm internally-matched HJFET has delivered 38.9 dBm (7.8 W) output power with 46% PAE and 11.6 dB linear gain at 12 GHz with a drain bias of 13 V. This is the first report of higher than 10 V operation of an X- and Ku-band power HJFET with the excellent power performance.

This paper presents Super-CMOS SRAM process technology that integrates bipolar and CMOS transistors in a chip while adding only one ion implantation step and no lithography mask steps to the conventional CMOS SRAM process. The Super-CMOS SRAM process therefore has the same process cost as the CMOS SRAMs, while it achieves higher access speeds. In order to demonstrate the Super-CMOS SRAM, we have developed a 3.3 V/5 V 256 kb SRAM using 0.4 µm Super-CMOS process technology. By applying bipolar transistors to the sense amplifier circuits, a high-speed access time of 5.8 ns with a 3.0 V power supply is successfully achieved.

For low-voltage, high-speed operation of LSIs, the most attractive features in fully-depleted (FD) SOI devices are their steep subthreshold slope and reduced drain junction capacitance. This paper discusses the impact of these features on circuit performance. FD SOI devices can have a threshold voltage of more than 100 mV lower than that of bulk devices within the limits of acceptable off-state leakage current. Thus they hold higher driving current even at supply voltages of less than 1 V. On the other hand, the reduced junction capacitance is effective to suppress the total parasitic capacitance especially in lightly loaded CMOS circuits. These attractive features improve the speed performance in FD SOI circuits remarkably at supply voltages of less than 1 V. For high-speed circuit applications, 0.25-µm-gate SIMOX circuits, such as frequency dividers, prescalers, MUX, and DEMUX, can operate at up to 1-2 GHz even at a supply voltage of 1 V. CMOS/SIMOX logic LSIs also exhibit better performance at very low supply voltages. At merely 1 V, a SIMOX logic LSI could be functional at up to 60-90 MHz using 0.26-0.34 µW/MHz/Gate of power dissipation. Furthermore, SIMOX logic LSIs will allow 20-30 MHz operation at 0.5 V of a solar cell with reasonable chip size. These investigations lead to the conclusion that FD CMOS/SIMOX technology will have a large impact on the development of low-voltage high-performance LSIs for portable digital equipment and telecommunication systems.

An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.

This paper describes an analytic method, experimental results and simulation results for self-heating in a SOI (Silicon On Insulator) high voltage MOS transistor. The new analytic method enabled the temperature-rise caused by self-heating to be measured precisely. The temperature-rise in an operating transistor was evaluated by measuring the change of the source current against the source current without the self-heating. In advance, the relation between the temperature-rise and the current change had been prepared by measuring the current decrease when the hot-chuck temperature had been changed in iso-thermal condition. By using this method, the dependence of the temperature-rise or the current decrease on the operating condition or the thermal resistance were clarified. Furthermore, these measurement results and the thermal resistance which is calculated by a FEM analysis enabled a fully coupled electrothermal device simulation to be analyzed more precisely. The dependence of the current decrease on the buried oxide thickness were also calculated.

A high-speed silicon-on-insulator (SOI) of a 1/8 frequency divider and a 64-bit adder were realized using an optimized gate-overlapped LDD and a self-aligned titanium silicide (TiSi2) source-drain structure. The advantages of the delay time and power consumption were analyzed by circuit simulation. The maximum operation frequency of the SOI divider is 2.9 GHz at 3.3 V. The SOI divider operates about 1.6 times faster than the bulk-Si divider. The power consumption of the SOI divider at the maximum operating frequency is about 60% of that of the bulk divider. On the other hand, the speed of the SOI adder is 1.9 nsec at 3.3 V. The SOI adder speed is about 1.3 times faster than the bulk adder. The power consumption of the SOI adder is about 80% of that of the bulk divider. It was found that the high speed, low power features of the SOI divider were due to the pass transistor which had low junction capacitance and little substrate bias effects, in addition to the low wiring capacitance and low fanout capacitance compared to the bulk adder. As a result, it is suggested that SOI circuits using pass transistor have a potential for GHz level systems and it is expected they will be applied to handy communication systems and portable computers used in the multimedia era.

In a fully depleted (FD) CMOS/SIMOX device, the threshold voltage can be reduced by 0.1 V while keeping the same off current as that of bulk CMOS. This enhances gate speed at low supply voltage so that lowering supply voltage reduces both active and static power consumption without additional circuits. An LSI architecture featuring a low supply voltage for internal gates and an LVTTL interface is proposed. However, to implement the architecture with FD-CMOS/SIMOX devices, there were problems which were low drain-breakdown voltage and half electrostatic discharge (ESD) hardness compared with that of bulk CMOS devices. An LVTTL-compatible output buffer circuit is developed to overcome the low drain-breakdown voltage. Cascade circuits are applied at an output stage and a voltage converter with cross-coupled PMOS is used for reducing the applied voltage from 3.3 V to 2.2 V or less. Using this output buffer together with an LVTTL-compatible input buffer, external 3.3 V signal can be converted from/to 2.0-1.2 V signal with little static current. The cascade circuit, however, weakens the already low ESD hardness of the CMOS/SIMOX circuit. The new ESD protection circuit provides robust LVTTL compatible I/O circuits. It features lateral diodes working as drain-well-diodes in bulk CMOS and protection devices for dual power supplies. A diode/MOS merged layout pattern is used for both to dissipate heat and save area. The CMOS/SIMOX ESD protection circuit is the first one to meet the MIL standard. Using 120 kgate test LSIs made on 300 kgate array with 0.25-µm CMOS/SIMOX, 0.25-µm bulk CMOS and 0.5-µm bulk CMOS, power consumptions are compared. The 0.25-µm CMOS/SIMOX LSI can operate at an internal voltage of 1.2 V at the same frequency as the 0.5-µm LSI operating at 3.3 V. The internal supply voltage reduction scheme reduces LSI power consumption to 3% of that of 0.5-µm bulk LVTTL-LSI.

The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.

We have designed a new current-mode low-voltage, low-power, high-frequency CMOS VCO circuit. The main purpose of this new circuit is to obtain operational capabilities with more than 1 GHz oscillation frequency from one battery cell. The current-mode approach was adopted throughout the circuit design to achieve this. New differential-type delay cells in the current-mode operation enable extremely low supply voltage operation and superior linearity between the oscillation frequency and control voltage of a ring oscillator. A design which combines the transitions of each delay cell output enables the VCO's high-frequency operation. To obtain a sufficient current level at output, a current amplifier with a small amount of positive feedback is used. The unnecessary generation of spectral components caused by mismatched time delay of delay cells in a ring-oscillator, which is an inherent problem of the VCO in a ring-oscillator form, is 0also analyzed. The characteristics of the designed VCO were examined by the SPICE circuit simulation using standard CMOS 0.6µm devices. Operation with a 1 V power supply, 1 GHz oscillation frequency, and 5.7 mW power dissipation was verified.

BiCMOS circuits using a base-boost technique for low-voltage application have been proposed. These circuits can operate at supply voltages down to 1.5 V. Their power dissipation, however, is 1.5-2 times of that of the CMOS circuit. We propose a novel BiCMOS circuit dissipating less power than that of conventional circuits. A base-boost technique is a key to low-voltage operation, and a gate holding the output voltage and a depletion nMOS pre-charge transistor are also introduced to reduce the power dissipation. Results of simulations using 0.3µm BiCMOS device parameters show that base-boosted BiNMOS (BB-BiNMOS) circuit is 1.5 times faster than CMOS circuit even at 1 V and that its power dissipation is almost the same power as that of a CMOS circuit, the base-boosted BiCMOS (BB-BiCMOS) circuit is twice as fast and dissipates only 1.2 times as much power. The energy-delay product of the BB-BiCMOS circuit is smaller than that of conventional BiCMOS circuits and is about half of that of a CMOS circuit, the BB-BiCMOS circuit is thus the most promising high-speed circuits for low-voltage and low-power applications.

A design methodology of high performance deep submicron CMOS in very low voltage operation has been proposed from low power dissipation point of view. In low voltage operation, threshold voltage is restricted by performance, stability of CMOS circuits and power dissipation caused by standby and switching transient current. As a result, threshold voltage is established to be 0.15 V even at 1 V operation from these requirements. Moreover, according to this design, 0.15 µm CMOS was fabricated with reduction of parasitic effects. It achieved propagation delay time 50 psec at 1 V operation. This results confirms that this design methodology is promising to achieve high performance deep submicron CMOS devices for low power dissipation.

This paper proposes a small 1/4Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F2 size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.

We describe low supply voltage analog circuit techniques for voice- and audio-band interfaces. These techniques can lower the supply voltage to 1 V, which is the voltage of a one-NiCd-cell battery. We have applied them in a swingsuppression noise-shaping method, and using this method, have fabricated A/D and D/A converters for the voice and audio bands. These converters operate with a 1 V power supply and have 13-bit and 17-bit accuracy in the audio-band and power consumption of about 1 mW. This performance proves that our techniques are sufficient for baseband analog interfaces.

Very-low-voltage 1.2-V mixed-signal CMOS technology is a device/circuit solution aimed at ultra-low-power portable systems such as digital cellular terminals and PDAs. We have developed an experimental 1.2-V mixed analog and digital LSI circuit/device technology. This technology is based on a new transistor structure that has a 0.3-µm gate length and a low Vth of 0.4 V, and that suppresses the short-channel effect. In this paper, we will mainly discuss low-voltage analog circuit design that uses this technology. We show that low Vth is essential not only to digital circuits, but also to 1.2-V analog amplifier, A/D converter and analog switch designs. To achieve high-conversion rate A/D converters, a pipeline architecture is used for low-voltage operation. To increase the attainable gain-bandwidth of the operational amplifier of the converter, a feedforward phase-compensated three-stage amplifier is proposed. The addition of a feedforward capacitor allows a high frequency signal to pass directly to the second stage, which optimizes use of the second stage bandwidth. Pole-zero canceling is used to achieve a fast settling of the amplifier. Although gain precision is degraded by the positive feedback through the feedforward capacitor, this can be offset by increasing the equivalent second-stage gain with an inner feedforward compensated amplifier. The gain-bandwidth of the proposed double feedforward amplifier is two to three times wider than with the conventional Miller compensation. With these techniques, we used 1.2-V mixed-signal CMOS technology to create a basic logic gate with a 400-ps delay and 0.4-µW/MHz power, and a 9-bit 2-Msample/s pipeline A/D converter with power dissipation of only 4 mW.

A new GaAs negative voltage generator suitable for biasing a GaAs MESFET power amplifier has been successfully developed and applied to a 1.9-GHz single-chip transmit/receive (T/R)-MMIC front-end including a power amplifier, a T/R-switch, and so on. To meet various requirements necessary for integration with a power amplifier, four new circuit techniques are introduced into this generator: (1)complementary charge pump operation to suppress spurious outputs. (2)an SCFL-to-DCFL cross-coupled level shifter to ensure a wide operation voltage range, (3)a level control circuit to reduce output voltage deviation caused by output current, and (4)interface and layout designs to achieve sufficient isolation between the power amplifier and the generator. The generator was incorporated into the MMIC front-end, and it was tested with a 30-lead shrink small outline package. With 20-to-500-MHz external input signals of more than -15 dBm, the generator produces negative voltages from -1.0 to -2.6 V for a wide range of suppiy voltages from 1.6 to 4.5 V. The current consumption is as low as 3.2 mA at 3 V. When a 22-dBm output is delivered through the power amplifier biased by the generator, low spurious outputs below -70 dBc are achieved. and gate-bias voltage deviations are suppressed to within 0.06 V even when a gate current of -140 µA flows through the amplifier. The generator also enables high speed operation of charge time below 200 ns, which is effective in TDMA systems such as digital cordless telephone systems. In layout design, electromagnetic simulation was utilized for estimating sufficient isolation between circuits in the MMIC. This negative voltage generator and its application techniques will enable GaAs high-density integration devices as well as single voltage operation of a GaAs MESFET power amplifier.

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

For high frequency video signals, display monitors for personal computers are required to shift from the horizontal scanning frequency fH=15.75 kHz for conventional TV broadcasting to fH=64 to 80 kHz, which is called XGA. Shifting to high frequencies and restrictions on the withstand voltage of horizontal transistors decrease the inductance of deflection yokes, which is an obstacle in manufacturing deflection yokes. A study was undertaken on an operation to permit deflection/high voltage integrated operation while keeping the inductance of the deflection yoke high. This paper reports the results.

The principles and design of current sense amplifiers for low-voltage MOS memories are described. The low input impedance of current sense amplifiers is explained using a simple model consisting of negative and positive resistance. A description of the model realized by a common-gate MOS amplifier employing transconductance enhancing techniques is also given. Some current sensing schemes for low-voltage ROM's and/or SRAM's are shown. For SRAM application, a current sensing scheme employing large-gain inverter-type amplifiers is proposed. A test chip including SRAM macrocells was designed and fabricated with 3.3-V 0.5-µm CMOS technology. An SRAM using current sense amplifiers was able to demonstrate that current sensing suppressed bitline delay to half that in conventional current-mirror types. The current sense amplifier had the same operating limit as the current-mirror type for low supply voltages. The measured operating limit of the STSM in this work was 1.3-V for threshold voltages of 0.55-V(n-channel) and -0.65-V(p-channel).

A 2V/120 ns flash EEPROM embedded in a microcontroller has been fabricated in 0.8 µm double-metal CMOS process technology with a simple stacked gate memory cell. To achieve low voltage and high speed operation, novel circuit technology and architecture; (a) PMOS-precharging NMOS-self-boost word line circuit with a higher voltage selector, (b) new erase algorithm for reverse operation, (c) column gate boost circuit, (d) hard-verify mode for replacing weak cells, (e) efficient redundancy of row and column lines, have been developed. A 512 kb flash EEPROM core chip incorporating these circuit techniques and architecture operate at 1.8 V and accesses data in 120 ns at 2 V and 70.

A family of single-switch ZVS-CV (Zero-voltage switchingclamped voltage) dc-to-dc converters is presented. This class of converter is realized by employing a commutation inductor circuit which is connected in parallel with either the transistor or the freewheeling diode in a conventional PWM converter. The technique described here is simple and output-voltage control is easy. The converters that comprise this family are derived form Buck, Boost, Buck/Boost, Cuk, Sepic and Zeta PWM converters. The steady-state characteristics of these converters such as the voltage conversion ratio, the ZVS conditions, and the input and output current ripples are analyzed. The analysis is confirmed by experiment.