At the sliding contact of brush and rotating slip-ring or commutator, it has been recognized that the brush wear is influenced by brush pressure, current density and atmosphere nearby contact part. However, little is known about the relation between brush wear and atmosphere condition in detail. In this paper, the experiments are carried out with a great attention to the effect of surrounding temperature and humidity on brush wear. The sliding part of brush and slip-ring is put on the sealed box and the atmosphere in the sealed box is kept on the specified condition by temperature and humidity control system. The brush wear, contact voltage drop and slip-ring surface morphology are observed after the sliding test. From these results, in both cases of the high humidity (nearby 80%) and low humidity (nearby 20%), the brush wear are large. And the brush wear rate is the lowest around 60% relative humidity. However, the characteristics of brush wear under the 15C is not similar to others. When the surrounding temperature is changed, in case of the 20% humidity, the brush wear increases with increasing surrounding temperature. On the other hand, in case of 80% humidity, the brush wear increases with decreasing surrounding temperature. Consequently, the results clearly shows that the temperature and humidity not only affect the brush wear but also change the condition of the film formation on slip-ring.

In this paper, new linearization techniques for low-voltage bipolar OTAs using hyperbolic function circuits are described. First, a design of an exponential-law circuit, which is a basic building block to compose hyperbolic sine and hyperbolic cosine circuits, is proposed. This circuit is simpler than the conventional circuit and is suitable for low-voltage application. Next, two linearized OTAs using the hyperbolic function circuits are presented. The transconductance is given by maximally flat approximation. Although designs of the OTAs are different, the output currents are given by the same expression. Finally, performance of the OTAs is discussed. The linear input voltage range of the proposed OTAs is almost the same as that of the conventional OTA. However, one of the proposed OTA has no more than two-thirds the power dissipation of the conventional one. The other has a superior high-frequency characteristic.

In this paper, the suppression of induced voltage on a printed wiring board through impedance loading by inserting impedance devices such as ferrite beads is focused on. How the suppression effect changes according to the insertion position of such devices is also investigated. Electromagnetic-field simulations were used to determine the distribution of voltage and current induced in wiring when a printed wiring board is exposed to an external electromagnetic field. Then, on the basis of these distributions, electromagnetic-field simulations were performed, and experiments were conducted to investigate the relationship between the insertion position of impedance devices and their suppression effect. It was verified that induced voltage can be large when a mismatch occurs between the impedance at the two ends of printed wiring, and that the suppression effect can differ significantly according to where an impedance device is inserted. A large effect was obtained by inserting an impedance device at a point 1/4 wavelength in distance from the end of a wire where voltage is being induced. In addition, comparing the use of resistors with the use of chip ferrite beads as impedance devices revealed similar tendencies in both. The above behavior was confirmed by numerical analysis.

This paper presents a new technique for accurately modeling uni-directional High-Voltage lightly-doped- drain MOS (HV MOS) devices by extending the bi- directional HV MOS model and adopting a new parameter extraction method. We have already reported on a SPICE model for bi-directional HV MOS devices based on BSIM3v3. However, if we apply this bi- directional HV MOS model and its parameter extraction technique directly to uni-directional HV MOS devices, there are large discrepancies between the measured and simulated I-V characteristics of the uni- directional devices. This paper extends the bi- directional HV MOS model, and adopts a new parameter extraction technique. Using parameters extracted with the new method, the simulated I-V characteristics of the uni-directional n-channel HV MOS device match the measured results well. Since our method does not change any model equations of BSIM3v3, it can be applied to any SPICE simulator on which the BSIM3v3 model runs.

The technique used is based on thermal optical activity measurement of temperature combined with electric-field-induced polarization modulation of the input light. Quartz is used as the sensing element. A 1/4 wave plate is placed behind the quartz so that a single sensing head can simultaneously output two signals: one includes the Pockels effect for voltage measurement; the other optical activity for the temperature measurement. The operating principle of the sensor which detects voltage and temperature is presented theoretically and experimentally. The technique for separating voltage and temperature from the signals is analyzed theoretically and experimentally. It was found that the sensitivity of the voltage sensor to temperature depends on the magnitudes of voltage applied to it. To realize temperature compensation over a full range, two key parameters must be obtained: one is the response of the voltage sensor to temperature when the applied voltage is zero; another is the response of the sensing material to temperature when a certain voltage is applied. In the absence of electrogyration the effect of voltage on the temperature sensor may be neglected. The technique was demonstrated using a fiber-optic voltage sensor with temperature compensation. The sensor offered a voltage measurement range of 0-10 kV, and a temperature stability of 0.4% within the temperature range of 20-70.

This paper describes a method for estimating current and voltage distributions by scanning with a probe. The method takes advantage of the phenomenon that the coupling between the current and the probe varies with the direction of the probe. The current and voltage are estimated by calculating the probe vector output for each of four directions. Both the current and voltage vector distributions can thus be estimated at the same time by using a single probe. The estimated distributions in a digital IC package and a microstrip line showed that this method produces reliable results. The simple structure of the probe should make it easy to reduce its size.

This paper describes how voltage fluctuation in the DC power supply of a digital IC can be reduced, by means of molding the package-pin in a ferrite-resin composite. The voltage fluctuation of the DC power supply, when the input terminal was driven by a 40 MHz, 5 Vp-p pulse wave, was measured using an oscilloscope. Simultaneously, the voltage spectrum of the fluctuation was measured using a spectrum analyzer. As a result, the voltage fluctuation was decreased by about 50 % when the IC package-pins were molded in a ferrite-resin composite, in which the µiac of the ferrite powder equalled 100, and the powder content was 80 weight-%. In the same IC, there was the reduction effect of the voltage spectrum of the fluctuation was recognized in the frequency range 40 MHz to 1 GHz.

This paper reports the performance of an AC-voltage sensor with a LiNbO3 integrated retroreflective structure based on the Y-junction Mach-Zehnder interferometer. This structure is capable of realizing a low-cost sensor chip because of the small chip size and single optical-fiber connection. In the sensitivity and frequency response evaluation, detection sensitivities of 6.3 µ V / Hz have been measured with a frequency response from 6 Hz to 2 GHz. These measurement limitations were also analyzed theoretically and compared with the experimental results. This unique sensor enables precise voltage measurement in an EMI environment, even inside a computer.

A two-phase boosted voltage (VPP) generator circuit was proposed for use in giga-bit DRAMs. It reduced the maximum gate oxide voltage of pass transistor and the lower limit of supply voltage to VPP and VTN respectively while those for the conventional charge pump circuit are VPP+VDD and 1.5 VTN respectively. Also the pumping current was increased in the new circuit.

This paper describes the effect of lowering the supply voltage and threshold voltages on the energy reduction of an ultralow-voltage multi-threshold CMOS/SIMOX (MTCMOS/SIMOX) circuit. The energy dissipation is evaluated using a graph with equispeed and equienergy lines on a supply voltage and a threshold voltage plane. In order to draw equispeed and equienergy lines for ultralow-voltage circuits, we propose a modified energy-evaluation model taking into account a input-waveform transition-time of the circuits. The validity of the proposed energy-evaluation model is confirmed by the evaluation of a gate-chain TEG and a 16-bit CLA adder fabricated with 0.25-µm MTCMOS/SIMOX technology. Using the modified model, the energy-reduction effect in lowering the supply voltage is evaluated for a single-Vth fully-depleted CMOS/SOI circuit, a dual-Vth CMOS circuit consisting of fully-depleted low- and medium-Vth MOSFETs, and a triple-Vth MTCMOS/SIMOX circuit. The evaluation reveals that lowering the supply voltage of the MTCMOS/SIMOX circuit to 0.5 V is advantageous for the energy reduction at a constant operating speed.

A 10-bit 3-Msample/s multibit cyclic A/D converter for mixed-signal LSIs with a small chip-area of 1.5 mm2 and low power consumption of 10.8 mW with a 2.7-V power supply was realized using a 0.8-µm CMOS process. This ADC module is designed for high-speed servo-controller LSIs used in hard-disk-drive systems. We found that three-cycle cyclic conversion (four bit, three bit+(one redundant bit), and three bit+(one redundant bit)) was optimal for achieving 10-bit resolution with a small chip-area and low power consumption given a required conversion time of 0.33 µs. Our multipath architecture cut power consumption by 30% compared to conventional cyclic A/D converters. By adding one signal path between the residue amplifier and the four bit subADC, the settling timing requirement can be relaxed, and the amplifier's power consumption thus reduced.

This paper describes a sub 1-V low noise amplifier (LNA) fabricated using a 0.35 µm SOI (silicon on insulator) CMOS process. The SOI devices have high speed performance even at low operating voltage (below 1 V) because of their smaller parasitic capacitance at source and drain than those of bulk MOSs. A body of a MOSFET can be controlled by using a field shield (FS) plate. The transistor body of the LNA is connected to its gate. The threshold voltage of the transistor becomes lower due to the body-biased effect so that a large drain current keeps the gain high, and active-body control improves the 1-dB gain compression point. A gain of 7.0 dB and a Noise Figure (NF) of 3.6 dB are obtained at 1.0 V and 1.9 GHz. The output power at the 1-dB gain compression point is +1.5 dBm. The gain and the output power at the 1-dB gain compression point are higher by 1.2 dB and 2.9 dB respectively than those of a conventionally body-fixed LNA. A 5.5 dB gain is also obtained at the supply voltage of 0.5 V.

An OTA without a tail-current source is proposed for low power supply voltages. Only two MOSFET's are connected between power supply lines in order to operate under low power supply voltages. A few MOSFET's are added at the expense of eliminating the tail-current source of the conventional OTA. SPICE simulation is shown in order to evaluate the proposed circuits. As an application, a low-pass filter is realized by employing the proposed OTA's.

A tail current source is often employed for many analog building blocks. It can limit the increase of excess power. It can also improve CMRR and PSRR. In this paper, we propose a very high output impedance tail current source for low voltage applications. The proposed tail current source has almost the same output impedance as the conventional cascode type tail current source in theory. Simulation results show that the output impedance of the proposed circuit becomes 1.28 GW at low frequencies. Applying the proposed circuit to a differential amplifier, the CMRR is enhanced by 66.7 dB, compared to the conventional differential amplifier. Moreover, the proposed circuit has the other excellent merit. The output stage of the proposed tail current source can operate at VDS(sat) and a quarter of VDS(sat) of the simple current source in theory and simulation, respectively. For example, in the simulation, when the reference current IREF is set to 100µA, the minimum voltage of the simple current source approximates 0.4 V, whereas that of the proposed current source approximates 0.1 V. Thus, the dynamic range can be enlarged by 0.3 V in this case. The value is still enough large value for low voltage applications. Hence, the proposed tail current source is suitable for low voltage applications.

We have studied the characteristic trade-offs in low power and low voltage MOSFETs from the viewpoint of back-gate control and body effect factor. Previously reported MOSFET structures are classified into four categories in terms of back-gate structures. It is shown that a MOSFET with a fixed back-bias has only a limited current drive at low voltage irrespective of device structures, while current drive of a dynamic threshold MOSFET with body tied to gate is more enhanced with increasing body effect factor. We have proposed a new dynamic threshold MOSFET, electrically induced body (EIB) DTMOS, which has a very large body effect factor at low threshold voltage and high current drive at low supply voltage.

This paper proposes a realization of power factor function generator having an arbitrary base and power factor which are determined by the ratios of the currents provided from outside of the circuit. The circuit characteristics do not depend on any transistor parameters, temperature, and other environmental conditions. The circuit operation is based on current mode that has a capability of low power supply voltage operation below than 2.0 V. SPICE simulation has been carried out using 0.7 µm BiCMOS parameters and shows quite good transfer characteristics.

It is the purpose of this paper to review the generation of quantized voltage steps in Josephson-junctions, and also the recent practical application of these precise measurements. A 10-V Josephson-junction-array-voltage standard system has been established with a Josephson-junction-array, a phase-locked millimeter wave, and a precise null-detection system. Based on these technologies, the AC Josephson effect has been applied to other precise measurements such as DC error voltage of a multi-integrating analog-to-digital converter and for a pulse-width-modulation type precise voltage calibrator.

Linear signal analysis (LSA) is the conventional method of estimating the playback voltage and pulse width in linearly operating shielded GMR heads. To improve the accuracy of LSA, a new, highly precise LSA which includes the effect of the magnetization distribution in the medium and inhomogeneous biasing by domain control magnets, was developed. Utilizing this new LSA to calculate the playback waveforms, the calculated peak voltage and pulse width were compared with the experimental values and agreement within 10% was obtained. As the result of estimation using the new LSA, it is considered that the use of a vertical-type spin-valve head will make it possible to achieve a recording areal density of 40 Gb/in2.

A fully on-chip current controlled open-drain output driver using a bandgap reference current generator was designed for high bandwidth DRAMs. It reduces the overhead of receiving a digital code from an external source for the compensation of the temperature and supply voltage variations. The correct value of the current control register is updated at the end of every auto refresh cycle. The operation at the data rate up to 0.8 Gb/s was verified by SPICE simulation using a 0.22 µm triple-well CMOS technology.

For the realization of low-voltage full-color FEDs, requirements for phosphor for the FED are proposed. Especially, the influence of released gases or substances from phosphors on the field emission within the FED was made clear. It was clarified that the analysis of F-N plots of the V-I curve of field emission characteristics was helpful to know the interaction of field emission and phosphors. In the experiment, we first obtained the depth from the phosphor surface of the low voltage electron excitation in case of ZnGa2O4, where the region available for cathodoluminescence at the anode voltage of 400 V is about 63 nm deep from the surface. The characteristic of the 12.4 cm-320(trio)240 pixels low-voltage full-color FED is reported. The luminance of 154 cd/m2 was attained at the anode voltage of 400 V and the duty factor of 1/241. Supported by the high potential of the FED as a flat panel, each problem shall be steadily solved to secure the firm stand as a new full color flat display in new applications.