In this paper, we describe a feed-forward dynamic voltage/clock-frequency control method enabling low power MPEG4 on multi-regulated voltage CPU with combining the characteristics of the CPU and the video encoding processing. This method theoretically achieves minimum low power consumption which is close to the hardware-level power consumption. Required processing performance for MPEG4 visual encoding totally depends on the activity of the sequence, and high motion sequence requires high performance and low motion sequence requires low performance. If required performance is predictable, lower power consumption can be achieved with controlling the adequate voltage and clock-frequency dynamically at every frame. The proposed method in this paper is predicting the required processing performance of a future frame using our unique feed-forward analysis method and controlling a voltage and frequency dynamically at every frame along with the forward analysis value. The simulation results indicate that the proposed feed-forward analysis method adequately predicts the required processing performance of every future frame, and enables to minimize power consumption on software basis MPEG4 visual encoding processing. In the case that CPU has Frequency-Voltage characteristics of 1.8 V @400 MHz to 1.0 V @189 MHz, the proposed method reduces the power consumption approximately 37% at high motion sequences or 65% at low motion sequences comparing with the conventional software video encoding method.

In low-power embedded processors design, stand-by power constraint is also important with average power and operation frequency. Multi-threshold-voltage cells are used in the design and the ratio of low-Vth cells should be controlled. On the other hand, physical synthesis flow is indispensable to achieve high performance and short design time. This paper proposes a physical synthesis methodology under the restriction of maximum low-Vth cell ratio. The experimental results show that our method can achieve only 4 MHz slower logic within 5% margin of the target low-Vth ratio. We have applied this design flow in an application processor design and the designed processor demonstrates 360 MIPS at 200 MHz only with 80 mW at 1.0 V, namely 4500 MIPS/W and 4.2 mA leakage current without any power-cut mode.

We have developed a high-efficiency charge-pump power supply circuit with large output current capability for mobile equipment. However, during the commercialization phase, we found that the large inrush current of 270 mA at charge-pump circuit startup-time could cause problems. In this paper we analyze the mechanism that causes this inrush current, and we propose circuitry to reduce it. We show SPICE simulation and measurement results for our proposed circuitry that confirm its effectiveness. By incorporating this circuitry, startup-time inrush current was reduced to 30 mA.

A compact, low voltage, low power and wide output operating range CMOS exponential-control variable-gain amplifier has been presented. The gain control range of the proposed variable-gain amplifier can be about 50.7 dB while the maximum linearity error is about -1.09%. For the case of supply voltage VDD = 2 V, the maximum power dissipation is only 1.6 µW. The proposed circuit has been fabricated in a 0.5 µm 2p2m N-well CMOS process. Experimental results are given to confirm the feasibility of the proposed variable gain amplifier. The proposed circuit is expected to be useful in analog signal processing applications.

A new multiple-valued current-mode (MVCM) logic circuit using substrate bias control is proposed for low-power VLSI systems at higher clock frequency. Since a multi-level threshold value is represented as a threshold voltage of an MOS transistor, a voltage comparator is realized by a single MOS transistor. As a result, two basic components, a comparator and an output generator in the MVCM logic circuit can be merged into a single MOS differential-pair circuit where the threshold voltages of MOS transistors are controlled by substrate biasing. Moreover, the leakage current is also reduced using substrate bias control. As a typical example of an arithmetic circuit, a radix-2 signed-digit full adder using the proposed circuit is implemented in a 0.18- µm CMOS technology. Its dynamic and static power dissipations are reduced to about 79 percent and 14 percent, respectively, in comparison with those of the corresponding binary CMOS implementation at the supply voltage of 1.8 V and the clock frequency of 500 MHz.

This paper describes low voltage write driver with pulse adding circuit. The presented write driver is constructed from the main switch circuit with impedance matching and pulse adding circuits and a timing generator. The main switch circuit is voltage type driver with matching resisters for flexible lines between a write driver and a write head. For 1.2 Gbps operation, the flexible lines have to be treated as transmission lines. Furthermore, to achieve steep rise/fall edge, the pulse adding circuits to generate double of supply voltage, +3.3/-3 V, at rise/fall edge have been developed. The write driver was implemented using 0.35 µm BiCMOS process. The die size is 1.2 mm0.6 mm and the measured results achieved tr/tf of less than 0.25 ns, tp of 0.5 ns and Ip of 73 mA.

This paper describes an ultralow-power multi-threshold (MT) CMOS/SOI circuit technique that mainly uses fully-depleted MOSFETs. The MTCMOS/SOI circuit, which combines fully-depleted low- and medium-Vth CMOS/SOI logic gates and high-Vth power-switch transistors, makes it possible to lower the supply voltage to 0.5 V and reduce the power dissipation of LSIs to the 1-mW level. We overview some MTCMOS/SOI digital and analog components, such as a CPU, memory, analog/RF circuit and DC-DC converter for an ultralow-power mobile system. The validity of the ultralow-voltage MTCMOS/SOI circuits is confirmed by the demonstration of a self-powered 300-MHz-band short-range wireless system. A 1-V SAW oscillator and a switched-capacitor-type DC-DC converter in the transmitter makes possible self-powered transmission by the heat from a hand. In the receiver, a 0.5-V digital controller composed of a 8-bit CPU, 256-kbit SRAM, and ROM also make self-powered operation under illumination possible.

As semiconductor manufacturing technology advances, power dissipation and noise in scan testing have become critical problems. Our studies on practical LSI manufacturing show that power supply voltage drop causes testing problems during shift operations in scan testing. In this paper, we present a new testing method named MD-SCAN (Multi-Duty SCAN) which solves power supply voltage drop problems, as well as its experimental results applied to practical LSI chips.

A simple CMOS Vth-adjustment method for a common-source floating-gate MOSFET(FG-MOSFET) is proposed. The apparent threshold voltage Vtha of an FG-MOSFET can be defined by a reference voltage Vref and/or a reference current Iref being almost irrelevant to the pre-stored charge on the floating gate.

Indium tin oxide (ITO) films were deposited at a temperature below 50 by a low-voltage sputtering system. The sputtering voltage was fixed at 100 V and Ar, Kr, and Xe were used as the sputtering gases. Compared with the sputtering in Ar gas, the sputtering in Kr or Xe gas caused a significant suppression of crystallization of the deposited film and resulted in the formation of amorphous films. These films had much lower resistivities than the films deposited using Ar gas, since the Hall mobility of the films had a larger value. Typical Hall mobility and carrier density are 50 cm2/Vsec, and 51020 cm-3, respectively. This improvement was attributable to the reduction of high-energy particle bombardment to the film surface in the sputtering. These films are stable at a temperature below 150, and crystallization occurs at a temperature above 150.

A CMOS voltage-mode divider, which can operate for low supply voltage and low power dissipation, is presented in this paper. The proposed voltage-mode divider can be used to realize a pseudo-exponential function generator. The experimental results of the proposed voltage-mode divider show that, under the supply voltage VDD=2.5 V, the linearity error is less than 1.18% and the power consumption is only 102 µW. Also the proposed pseudo-exponential function generator exhibits a 15 dB output dynamic range and the linear error is less than1.54%. Both the proposed circuits have been fabricated in a 0.5 µm N-well CMOS 2P2M process. The proposed circuits are expected to be useful in analog signal processing applications.

Temperature dependence of drain current is analyzed in detail in terms of mobility and threshold voltage. From the analyses, it is proved that a point exists that the drain current is fixed without depending on temperature when the MOSFET operates in strong inversion. Applying this characteristic, a CMOS temperature-voltage converter operating in strong inversion with high linearity is proposed. SPICE simulation and experimental results are shown, and the corresponding performances are discussed.

A switched capacitor DC-DC voltage converter that has an arbitrary conversion ratio of rational number is presented. A given voltage conversion ratio is systematically expanded to construct a switched capacitor circuit that operates with a two-phase switching clock. The conversion ratio is completely free from capacitance values and ratios under the assumption that there is no charge transfer between the two switching phases. This means that the converter cannot supply any power to the load. This restricts the application of the converters to a very limited area such as a voltage reference generator that only provides a reference voltage and no power to a circuit. The conditions for the convergence of the output voltage and the stray capacitor effects are discussed. The output voltage error and required switching frequency are also discussed when the converter is used as a DC voltage supply source that provides power to a load.

Two new voltage-mode universal biquadratic filters each with three input signals and one output signal are presented. Each proposed universal biquadratic filter is composed of only two CCIIs, two capacitors and two resistors and can realize all the standard filter functions, that is, highpass, bandpass, lowpass, notch and allpass filters (one more active device is needed for the realization of allpass filter). The proposed circuits have good sensitivities performance and have no requirements for component-matching conditions.

By adding an auxiliary transformer to a single-stage single-switch power-factor-corrected converter (S4PFCC), the storage capacitor voltage and its range of voltage change against line voltage change are reduced. In addition, this transformer provides a direct power transfer path for input line to output load to increase the conversion efficiency. High power factor is maintained due to the elimination of dead angle of the input current. This paper presents detailed analysis and optimal design of a discontinuous conduction mode (DCM) boost-flyback S4PFCC with the auxiliary transformer. Experimental results for a 15 V/60 W prototype and with comparison to a S4PFCC without the auxiliary transformer are given to show the proposed approach effective.

This paper presents a variable pipeline depth processor, which can dynamically adjust its pipeline depth and operating voltage at run-time, we call dynamic pipeline and voltage scaling (DPVS), depending on the workload characteristics under timing constraints. The advantage of adjusting pipeline depth is that it can eliminate the useless energy dissipation of the additional stalls, or NOPs and wrong-path instructions which would increase as the pipeline depth grow deeper in excess of the inherent parallelism. Although dynamic voltage scaling (DVS) is a very effective technique in itself for reducing energy dissipation, lowering supply voltage also causes performance degradation. By combining with dynamic pipeline scaling (DPS), it would be possible to retain performance at required level while reducing energy dissipation much further. Experimental results show the effectiveness of our DPVS approach for a variety of benchmarks, reducing total energy dissipation by up to 64.90% with an average of 27.42% without any effect on performance, compared with a processor using only DVS.

We have obtained high performance and low voltage driving OCB panel by reducing the critical voltage and retardation matching between liquid crystal layer and compensation films. Flattening color filter layer and optimizing rubbing process have minimized the critical voltage in the panel. In addition, an appropriate retardation of the film and LC layer has scanned to achieve low driving voltage and high transmission. Especially, by adopting new driving scheme, we considerably reduced the initial bend transition time, which is known as one of drawbacks in OCB mode. As a result, we developed the proto-type 17" WXGA OCB panel with less than 5 V drive, over 90% of TN light efficiency and over 80 degree for all viewing direction except for rubbing direction including color shift as well as high-speed response time.

We've been developing new electron guns for a high brightness CRT. The electron guns were modified to increase the emission current without the increase of the driving voltage. We achieved the high brightness CRT with "low cut-off electron gun" and the gun was successfully introduced into our multimedia CRT. Now we are developing next generation gun or "double drive electron gun" for larger screen CRT. The gun can emit about double current in comparison with the "low cut-off electron gun."

This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 µm 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure, the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11 V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.

DC and RF performances of AlGaN/GaN HEMTs are simulated using a two-dimensional device simulator with the material parameters of GaN and AlGaN. The cut-off frequency is estimated as 205 GHz at the gate length of 0.05 µm and the drain breakdown voltage at this gate length is over 10 V. The values are satisfactory for millimeter wavelength power applications. The use of thin AlGaN layers has key importance to alleviate gate parasitic capacitance effects at this gate length.