A family of single-switch ZVS-CV (Zero-voltage switchingclamped voltage) dc-to-dc converters is presented. This class of converter is realized by employing a commutation inductor circuit which is connected in parallel with either the transistor or the freewheeling diode in a conventional PWM converter. The technique described here is simple and output-voltage control is easy. The converters that comprise this family are derived form Buck, Boost, Buck/Boost, Cuk, Sepic and Zeta PWM converters. The steady-state characteristics of these converters such as the voltage conversion ratio, the ZVS conditions, and the input and output current ripples are analyzed. The analysis is confirmed by experiment.

SOI DRAM's are candidates for giga-bit scale DRAM's due to the inherent features of SOI structure, and are also desired to be used as low-voltage memories which will be used in portable systems in the forthcoming multimedia era. However, some drawbacks are also anticipated owing to floating substrate effects. In this report, the advantages and problems concerning SOI DRAM's were reconsidered by evaluation of our test devices and also by analysis with device and circuit simulators for their future prospects. The following advantages of SOI DRAM's were verified. Low-voltage operation, active current reduction and speed gain were obtained by the reduced junction capacitance and the back-gate-bias effect. Static refresh characteristics were improved due to the reduced junction area. Soft error immunity was improved greatly by the complete isolation of the active region when the body potential is fixed. The problems that need to be resolved are closely related to the floating substrate effect. The soft error immunity in a floating body condition and the dynamic refresh characteristics were degraded by the instability of the floating body potential. Process and device approaches such as the field-shield-body-fixing method as well as circuit approaches like the BSG scheme are required to eliminate the floating substrate effects. From these investigations it can be said that a low-voltage DRAM with a current design rule would be possible if we pay close attention to the floating-substrate-related issues by optimizing various process/device and circuit techniques. With further development of the technology to suppress the floating substrate effects, it will be possible to develop simple and low-cost giga-bit level SOI DRAM's which use the SOI's inherent features to the full.

This paper clarified fundamental aspects of both triboelectric processes and electrostatic discharge (ESD) phenomena to the electronic systems. A chance for ESD can occur if a charged metal object (steel piped chair, for example) contacts or collides with another metal objects at moderate speed. At metal-metal ESD event, the metal objects act as a radiation antenna in a very short time (some 100ps, for example) which emanates impulsive electromagnetic fields with unipolarity into the surrounding space. Because of ESD at low-voltage (3kV or less) conditions, the direction of electrons movement at the spark gap is always unidirectional and fixed. The spark gap works as a momentary switch and also as a "diode." The dominant fields radiated from the metal objects are impulsive electric fields or impulsive magnetic fields which depend on the metal object's electrical and geometric conditions. This impulsive electromagnetic fields penetrate electronic systems, causing electromagnetic interference (EMI) such as malfunctions or circuit upset. The difference between EMI actions in high-voltage ESD and low-voltage ESD is experimentally analyzed in terms of energy conversion/consumption. A series of experiments revealed that EMI actions due to the metal-metal ESD are not proportional to the charge voltage nor the discharge current. In order to capture single shot impulsive electromagnetic fields very close to the ESD point (wave source), a short monopole antenna as an ultra broad-band field sensor was devised. As for signal transmissions between the short monopole antenna and the instrument (receiver), micro/millimeter wave techniques were applied. The transmission line's minimum band width DC-18.5GHz is required for time domain measurements of low-voltage ESD.

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0.25 µm n-AlGaAs/i-InGaAs HJFET process operates at up to 10 Gbps with power consumption as low as 19 mW at a supply voltage of 1.3 V.

The degradation of I-V characteristics under constant emitter-base reverse voltage stress in advanced self-aligned bipolar transistors was analyzed. Experimental analyses have been taken the stress field effect into account when predicting hot-carrier degradation. These analyses showed that base current starts to increase when the reverse voltage stress is about 3 V. The dependence of the base current change on reverse voltages of more than 3 V was also investigated experimentally, and equations expressing hot-carrier degradation in terms of the exponential dependence of excess base current on both reverse stress voltage and stress-enhancing voltage related to emitter-base breakdown voltage were derived.

Threshold voltage shift in high frequency operation of 0.3µm and 0.35µm gate SOI CMOS is experimentally studied, using supply current measurement of inverter chains as test structures. The threshold voltage shift is obtained from the measurement of the leak currents in DC and high frequency condition. For a large supply voltage the electron-hole generation current becomes dominant, resulting in lowered threshold voltage, while the threshold voltage becomes higher than DC case for a low supply voltage. A reasonable relation of the threshold voltage shift and average electric field in the channel is obtained in this study. This method will be useful as a measure of "substrate current" for floating body SOI CMOS.

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great dfficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 µm device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.

This paper surveys trends in and prospects for low power LSI circuits technologies for portable terminal equipment, in which low-voltage operation of LSIs will be emphasized because this equipment will be battery-powered. Since this brings about serious operation speed degradation of LSIs, however, it will become more and more important how to operate them faster under low-supply voltage. We propose two new circuit techniques that make it possible to operate LSIs at high speed even when the supply voltage is very low (1-2 V corresponding to one or two battery cells). The new low-voltage RF LSI circuit technique, developed using silicon bipolar technology and using a novel current-folded mixer architecture for the modulator, result in a highly linear modulator that operates at 2 V. Its power consumption is less than 2/3 that of previously reported ICs. And for a low voltage baseband LSI we propose the multi-threshold CMOS (MTCMOS) technique, which uses two sets of threshold-voltage levels so that the LSI can operate at high speed when driven by a 1-V power supply. The multi-threshold CMOS architecture enabled us to create LSIs that operate faster than conventional CMOS circuits using high-threshold-voltage MOSFETs. When operating with a 1-V power supply, our LSIs are three times faster than the conventional ones.

With the fully depleted ultra-thin-film SOI CMOS, one important issue is controlling the threshold voltage (Vth) while maintaining high speed operation and low power consumption. To control the Vth, applying a bias voltage to the substrate is one of the most practical methods. We suggest a fully depleted ultra-thin-film SOI CMOS with a floating back gate, which is formed at the lower part of the channel field inside the substrate and stores electrons injected into it. This device can eliminate the necessity of an extra circuit or a separate power supply to apply a negative voltage. The silicon wafer direct bonding technique is used to construct this device. With the prototyped devices, we can successfully control the Vth for both the nMOSFET and pMOSFET at around 0.5 V by controlling the quantity of the electric charges injected into the floating back gate.

A new low-power and high-speed CMOS interface circuit is proposed in which signals are transmitted by means of impulse voltage. This mode of transmission is called impulse transmission. Although a termination resistor is used for impedance matching, the current through the output transistors and the termination resistor flows only in transient states and no current flows in stable states. The output buffer and the termination resistor dissipate power only in transient states, so their power dissipation is reduced to 30% that of conventional low-voltage-swing CMOS interface circuits at 160 MHz. The circuit was fabricated by 0.5 µm CMOS technology and was evaluated at a supply voltage of 3.3 V. Experimental results confirm low power of 4.8 mW at 160 MHz and high-speed 870 Mb/s error free point-to-point transmission.

This paper describes ALINX (Advanced Low-voltage Interface Circuit System), a low-power and high-speed interface circuit of submicron CMOS LSI for digital information and telecommunications systems. Differential and single-ended ALINXs are low-voltage swing I/O interface circuits with less than 1.0 V swing from a 1.2 V supply. Specifically, the differential ALINX features a pair of complementary NMOS push-pull drivers operating from a 1.2 V supply, reducing power consumption compared to conventional high-speed interface circuits operating from a 5 V or 3.3 V supply. The DC power consumption is approximately 11% of ECL. We observed 622 Mbps differential transmission with 8 mW power consumption and single-ended transmission at 311 Mbps with 14 mW with a PN23 pseudo-random pattern. We also describe a noise characteristic and ALINX applications to high-speed data buses and LSI for telecommunications systems. A time/space switch LSI with 0.9 W total power consumption was fabricated by 0.5 µm CMOS process technology. This chip can use a plastic QFP.

A direct calculation method of efficiency and power of FETs from d.c. characteristics determined by knee and breakdown voltages is proposed to make clear the requirements for knee and breakdown voltages of FETs under low-voltage operation of power amplifiers. It is shown from the calculation that the breakdown voltage has a greater effect on power and efficiency than the knee voltage and has to be three or more times of the operating voltage in order not to degrade efficiency under class-AB operation. A 3.3 V UHF-band 3-stage high efficiency and high power monolithic amplifier has been developed with the use of power FETs satisfying the requirements for knee and breakdown voltages under low-voltage operation. A power-added efficiency of 57.3% and a saturated output power of 31.8 dBm have been achieved for a drain voltage of 3.3 V in UHF-band. The direct calculation method of efficiency and power from d.c. characteristics, which can provide the required knee or breakdown voltage for a given efficiency, power, or bias conditions, is considered to be useful for developing power devices with various requirements for efficiency, power, and bias conditions.

This paper describes 950 GHz power performance of double-doped AlGaAs/InGaAs/AlGaAs heterojunction field-effect transistors (HJFET) operated at a drain bias voltage ranging from 2.5 to 3.5 V. The developed 1.0 µm gatelength HJFET exhibited a maximum drain current (Imax) of 500 mA/mm, a transconductance (gm) of 300 mS/mm, and a gate-to-drain breakdown voltage of 11 V. Operated at 3.0 V, a 17.5 mm gate periphery HJFET showed 1.4 W Pout and -50.3 dBc adjacent channel leakage power at a 50 kHz off-carrier frequency from 950 MHz with 50% PAE. Harmonic balance simulations revealed that the flat gm characteristics of the HJFET with respect to gate bias voltage are effective to suppress intermodulation distortion under large signal operation. The developed HJFET has great potential for small-sized digital cellular power applications operated at a low DC supply voltage.

This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.

The stability of a high-resistivity load SRAM cell using thin-film SOI MOSFET's was investigated as compared with bulk-Si MOSFET's. In SOI MOSFET's back-gate-bias effect was suppressed by indirect application of back-gate-bias to the channel region through the thick buried oxide. The Vt shifts were reduced to be 10% and 14% of that in bulk-Si MOSFET's in partially and fully depleted devices, respectively. The reduction of back-gate-bias effect provides improvement of "high" output voltage and gain in the enhancement-enhancement (EE) inverter in a high-resistivity load SRAM cell, thereby offering improved cell stability. It was demonstrated by using partially depleted SOI SRAM cells that non-destructive reading was obtained even at a low drain voltage of 1.4 V without gate-potential boost, which was much smaller than the operation limit in a bulk Si SRAM with the same patterns and dimensions used as a reference. This implies that SOI devices can also offer low-voltage operation even in TFT-load cells used in up-to-date high-density SRAM's. These results suggest that thin-film SOI MOSFET's have a superior potential of low-voltage operation expected for further scaled devices and/or for portable systems in a forthcoming multimedia era.

Recenty, the Josephson effect-based voltage standard has been realized by using the Josephson junction array which is constructed by integrating many Josephson junctions. In this article, the 1-V Josephson-junction-array voltage standard used in routine calibration work and further development of the 10-V Josephson junction array at the Electrotechnical Laboratory (ETL) are introduced.

A bipolar low-voltage multiplier core is presented. The proposed low-voltage multiplier core is built from a bipolar quadritail cell. Voltages applied to the individual bases of the transistors in the bipolar quadritail cell are aVxbVy, (a1)Vx(b1)Vy ,aVx(b1)Vy, and (a1)VxbVy, where Vx and Vy are the input signals, and a and b are constants, for example, VxVy, O, Vx, and Vy. Simple input systems using resistive dividers are also described. The dc transfer characteristics were verified on a breadboard using transistor-arrays and discrete components. The dc transfer characteristic of the proposed multiplier core is very close to that of the Gilbert multiplier cell, but the proposed multiplier core is operable on low supply voltage. Therefore, a bipolar multiplier core using a quadritail cell is a low-voltage version of the Gilbert multiplier cell. The proposed bipolar multiplier is practically useful because it can be easily implemented in integrated circuits by utilizing a multiplier core and a resistor-only input system, and it also operates at very lowvoltage. Therefore, the proposed bipolar multipliers are very suitable for low-power operation.

This study shows that using the direct offset integration technique (DOIT) and additional positive feedback (APF) in a high-Tc dc superconducting quantum interference device (SQUID) improves the effective flux-to-voltage transfer function and reduces the flux noise of a magnetometer, thus improving the magnetic field noise. The effective flux-to-voltage transfer function and the flux noise with APF were measured at different values of the positive feedback parameter βa, which depends on the resistance of the APF circuit. These quantities were also compared between conditions with and without APF. This investigation showed that a βa condition the most suitable for minimizing the flux noise of a magnetometer with APF exists and that it is βa=0.77. The effective flux-to-voltage transfer function with APF is about three times what it is without APF (93 µV/Φ0 vs. 32 µV/Φ0). The magnetic field noise of a magnetometer with APF is improved by a factor of about 3 (242 fT/Hz vs. 738 fT/Hz).

We propose and fabricate n+-p+ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, dispite a low channel doping concentration of 1015 cm-3, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19 µm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1 µm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.