We present excellent performance of a novel two-stage SiGe hetero-bipolar transistor (HBT) power amplifier (PA) in which different collector doping structures were employed for the first and second stages. A selectively ion implanted collector (SIC) structure was employed for the first stage HBT in order to obtain a high gain, while without-SIC structure was used for the second stage HBT in order to achieve a high breakdown voltage. At 1.95 GHz, the total PAE of 31% and a gain of 28 dB with an output power (Pout) of 26 dBm were obtained while the adjacent channel power ratio (ACPR) was less than -38 dBc for W-CDMA modulation signals.

DC and RF performances of AlGaN/GaN HEMTs are simulated using a two-dimensional device simulator with the material parameters of GaN and AlGaN. The cut-off frequency is estimated as 205 GHz at the gate length of 0.05 µm and the drain breakdown voltage at this gate length is over 10 V. The values are satisfactory for millimeter wavelength power applications. The use of thin AlGaN layers has key importance to alleviate gate parasitic capacitance effects at this gate length.

The fully integrated LC voltage controlled oscillator by 0.35 µm CMOS technology is demonstrated. It has 2 GHz oscillation frequency, 23.58 mW power consumption under 3 V biased and 9.1% frequency tuning. The layout optimization method of inductor to increase quality factor and also to reduce phase noise is used. A general method is proposed which is capable of making an effective prediction of F, device excess noise number, and acquiring the phase noise of oscillators accurately. From this proposed method, the low phase noise by calculation is attained. The phase noise of measured value which shows good match with calculating data is about -115.5 dBc/Hz at off set frequency 600 kHz.

Sliding contact behavior is important in the mechanism of collecting current. In this study, the effect of ambient gas including an inert gas on surface film formation and on the contact voltage drop was examined, changing the atmosphere from low pressure to atmospheric pressure. Furthermore, the sliding surface state was observed using SEM, EDX and XPS analyzers after the test operation. As a result, at the sliding contact in an inert gaseous environment (nitrogen and argon), it was confirmed that the contact voltage drop tends to increase. However, it was clarified that any chemically generated surface film is difficult to detect in the inert gas environment by qualitative analysis. On the basis of these results, we suggest the existence of physically adsorbed surface film. The relationship between inert gases and sliding contact phenomena is discussed.

In this paper, a Micro-Step-Separating System is realized for investigating phenomena of initial state of separating contacts. This system can control the contact separation in a discrete way with about 0.5 µm step. By using this system, we observed a relationship between contact voltage and contact separation gap. Ag contacts were observed. The observation showed that the contact voltage rose up and then fell down to the stable voltage at each step separation. From this observation, we expect to elucidate the contact bridge phenomena with more sophisticated way because we can approach them under the thermal equilibrium condition.

A voltage-controlled ring oscillator with an RC delay as an additional delay to vary the oscillation frequency is proposed. The use of MOS resistors provides a wide range tuning ability from 40 Hz to 366 MHz. The proposed circuit also enables implementation of a low frequency voltage-controlled ring oscillator with relatively smaller devices than the conventional one.

This paper describes the design of a 2.7 V operational, 200 MS/s, 14-bit CMOS D/A converter (DAC). The DAC consists of 63 current cells in matrix form for an upper 6-bit sub-DAC, and 8 current cells and R-2R ladder resistors for a lower 8-bit sub-DAC. A source degeneration resistor, for which a transistor in the triode operational region is used, is connected to the source of a MOS current source transistor in a current cell in order to reduce the influence of threshold voltage (Vth) variation and to satisfy the differential nonlinearity error specification as a 14-bit DAC. In conventional high-speed and high-resolution DACs that have the same design specifications described here, spurious-free dynamic range (SFDR) characteristics commonly deteriorate drastically as the frequency of the reconstructed waveform increases. The causes of this deterioration were carefully examined in the present study, finding that the deterioration is caused in part by the input-data-dependent time-constant change at the output terminal. Unexpected current flow in parasitic capacitors associated with current sources causes the change in the output current depending on the input data, resulting in time-constant change. In order to solve this problem, we propose a new output circuit to fix the voltage at the node where the outputs of the current sources are combined. SPICE circuit simulation demonstrates that 63 dB of SFDR characteristics for the 90 MHz reconstructed waveform at the output can be realizable when the supply voltage is 2.7 V, the clock rate is 200 MS/s, and the power dissipation is estimated to be 300 mW.

The low phase noise, low supply voltage 1.3 GHz CMOS VCO has been realized by 0.25 µm standard CMOS technology without any trimming and any tuning. The phase noise characteristics of -109 dBc/Hz and -123 dBc/Hz at 100 kHz offset and 500 kHz offset were achieved from carrier, respectively, with 1.3 GHz oscillation frequency at 1.4 V supply voltage. The performance of 1.4 V supply voltage phase noise was superior to that of 2.0 V supply voltage phase noise due to low output impedance current source. The tuning ranges of 13.3%, 16.6%, and 20.1% for 1.4 V, 1.8 V, and 2.0 V supply voltage were achieved, respectively. The amplifier consisted of one pair of PMOS differential stage with large gate length NMOS current source to realize low supply voltage operation and to avoid flicker noise contribution for phase noise. The on-chip spiral inductor consisted of three terminals arranged in a special shape to obtain high Q and small chip area. The power dissipation of this VCO was 22.4 mW without buffer amplifier.

We present a new multi-stage charge pump that is suitable for low-voltage operation, and in particular for low voltage flash memory. Compare to the Dickson charge pump and previously reported modified Dickson charge pumps, the proposed charge pump offers the improved pumping voltage gains. The proposed charge pump is composed of a pair of pumps and utilizes the internal boosted voltages of one side of the paired pumps as the charge transferring voltages to the other side. The simulated and measured results indicate that the proposed pump is highly efficient in overcoming both the pumping gain decrease and the current driving capability degradation caused by the threshold voltage of the charge-transfer gate.

A pass-transistor logic is enhanced with a bootstrap configuration for sub-1 V operation at high speed and low power. The bootstrap configuration drives the output to full swing, which accelerates the signal transition and cuts off the short-circuit current of subsequent CMOS logic gates. The asynchronous or synchronous timing sequence of the input (drain) and the control (gate) signals ensures bootstrap operation. A 1-b arithmetic logic unit (ALU) and an EXNOR gate built with the bootstrap pass-transistor logic outperforms those built with other types of pass-transistor logic. An experimental 16-b pass-transistor adder operates down to 0.4 V with a delay time of 4.2 ns and a power dissipation of 2.8 µ W/MHz at 0.5 V.

A linear voltage-to-current convertor without current mirror circuit is proposed for low distortion applications employing short channel MOSFET's. Twin current sources and current sinks pair of MOSFET's having the same drain-source voltage are employed for a substitute of the current mirror circuits, in order to eliminate the channel length modulation factor of the short channel MOSFET's. HSPICE simulation is shown in order to evaluate the proposed circuits. As an application, a low distortion OTA is realized by employing the proposed linear voltage-to-current convertor with short channel MOSFET's.

This paper describes an Embedded DRAM Hybrid Macro, which supports various memory specifications. The eDRAM module generator with Hybrid Macro provides more than 120,000 eDRAM configurations. This eDRAM includes a new architecture called Auto Signal Management (ASM) architecture, which automatically adjusts the timing of the control signals for various eDRAM configurations, and reduces the design Turn Around Time. An Enhanced-on-chip Tester performs the maximum 512b I/O pass/fail simultaneous judgments and the real time repair analysis. The eDRAM testing time is reduced to about 1/64 of the time required using the conventional technique. A test chip is fabricated using a 0.18 µm 4-metal embedded DRAM technology, which utilizes the triple-well, dual-Tox, and Co salicide process technologies. This chip achieves a wide voltage range operation of 1.2 V at 100 MHz to 1.8 V at 200 MHz.

We propose an effective dopant pile-up model which is useful for device optimization in a short-term. Our purpose is that the model provides speedy calculation for numerous simulations constructed by design of experiment (DoE), and the calibration is also easy in practical range of process condition. The dopant pile-up in the Si/SiO2 interface is calculated using a non-pair diffusion model that solves one equation for each impurity, considering an essential physics where RSCE is due to the dopant pile-up in the Si/SiO2 interface. A non-pair diffusion for dopants and point defects is adequate for time length which can ignore their reactions. The key for the modeling of RSCE is that the dependence on various processes such as channel implantation and annealing conditions can be reproduced in the local process window. The capability of the model is investigated though the comparison to measurements in actual n-channel MOSFETs for different process technologies. We also check the prediction accuracy of the dopant profiles using our model. As a result, the optimization of 4 parameters for 25 jobs based on DoE is possible less than 2 hours using our model.

A new analysis method for random dopant induced threshold voltage fluctuations by using Monte Carlo ion implantation were presented. The method was applied to investigate Vt fluctuations due to statistical variation of pocket dopant profile in 0.1µm MOSFET's by 3D process-device simulation system. This method is very useful to analyze a statistical fluctuation in sub-100 nm MOSFET's efficiently.

A three inputs and single output voltage-mode universal biquadratic filter using only two operational transconductance amplifiers (OTAs) and two capacitors is presented. The new circuits offer several advantages, such as employing the minimum number of active and passive components (two OTAs and two capacitors), the versatility to synthesize highpass, bandpass, lowpass, notch and allpass responses without component matching conditions, high input impedance for bandpass and lowpass filter realizations and good sensitivities performance.

In this paper, we propose a floating resistor circuit with positive and negative resistance operating at the low supply voltages 1.5 V. Only two transistors are connected between supply lines in order to operate under the low power supply voltages. In this circuit, current subtraction is carried out at the gate terminal for which input/output voltage is applied. As a result, the proposed circuit can realize the large range of resistance of positive and negative resistances. Therefore, in an application, the proposed circuit is used in neuro-based limit cycle generator as synaptic weights.

A mapping circuit in order to have a wider input dynamic range is proposed. MOSFET's connecting between power supply lines are employed to construct the mapping circuit. SPICE simulation is shown to evaluate the proposed circuits. With the proposed mapping circuit, two-MOSFET subtractor has a rail-to-rail input voltage. As an application, an OTA consisting of subtractors is realized by employing the proposed mapping circuits to have a rail-to-rail input voltage range.

This paper presents a 0.5Vdd-step pumping method for Dickson-type charge-pump circuits that achieve high overall efficiency, including regulator circuitry, even at large output currents, and these circuits are targeted at mobile equipment applications. We have designed positive and negative charge-pump circuits which use a 0.5Vdd-step pumping method, are implemented with advanced control functions, and are fabricated with our custom CMOS process. Measured results showed that efficiency of a 2.5-stage positive charge-pump circuit before regulation is more than 93% (power supply Vdd=5 V, output voltage Vout=16.9 V 3.5Vdd, output current Iout=4 mA), and that of a 1.5-stage negative charge-pump circuit is 93% (power supply Vdd=5 V, output voltage Vout=-7.2 V -1.5Vdd, output current Iout=4 mA).

The square-law characteristics of MOSFET in the saturation region have a parameter of threshold voltage VT. However, it introduces some complexities to the circuit design since it depends on kinds of MOS technology and cannot be controlled easily. In this paper, we show an equivalent MOSFET cell which has VT-programming capability and some application instances based on it. The simulation is carried out using CMOS 0.8 µm n-well technology and the results have shown the feasibility of the proposed structure.

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOSFET (FG-MOSFET) is proposed. First, the grounded VCLVR realization is discussed. The proposed circuit consists of only an ordinary MOSFET and an FG-MOSFET. The advantages of the proposed VCLVR are low-power and wide-input range and also the power consumption of the proposed VCLVR is the same as an ordinary passive resistor. The performance of the proposed circuits are confirmed by HSPICE simulations with a standard 0.6 µm CMOS process parameters. Simulations of the proposed VCLVR demonstrate a resistance value of 40 kΩ to 338 kΩ and an input range of 4.34 V within THD of less than 1.1%. Next, we proposed a new floating node linear variable resistor using the proposed VCLVR. The performance of the circuit is also evaluated through HSPICE.