We report here on the electrical and structural characteristics of InGaP/GaInAsN DHBTs with up to a 50 mV reduction in turn-on voltage relative to standard InGaP/GaAs HBTs. High p-type doping levels ( 3 1019 cm-3) and dc current gain (βmax up to 100) are achieved in GaInAsN base layer structures ranging in base sheet resistance between 250 and 750 Ω/. The separate effects of a base-emitter conduction band spike and base layer energy-gap on turn-on voltage are ascertained by comparing the collector current characteristics of several different GaAs-based bipolar transistors. Photoluminescence measurements are made on the InGaP/GaInAsN DHBTs to confirm the base layer energy gap, and double crystal x-ray diffraction spectrums are used to assess strain levels in the GaInAsN base layer.

This paper presents improved versions of three-stage positive-output and two-stage negative-output Dickson charge-pump circuits which are intended to replace switching regulators in video-product CCD driver applications (where 12 V and -6.5 V are needed), and are designed and fabricated in a custom CMOS process. From a power supply Vdd of 4.0 to 5.5 V, the positive charge pump generates a positive output voltage of greater than 3.9Vdd, while the negative charge pump generates a negative voltage of greater than -1.9Vdd, both with efficiencies of greater than 94% at 2 mA output currents.

We propose an effective model that can reproduce the reverse short channel effect (RSCE) of the threshold voltage (Vth) of MOSFETs using a conventional process simulator that solves one equation for each impurity. The proposed model is developed for local modeling which is effective within the limited process conditions. The proposed model involves the physics in which RSCE is due to the pile up of channel dopant at the Si/SiO2 interface. We also report the application to actual device design using our model. The calculation cost is much lower than for a pair diffusion model, and device design in an acceptable turn around time is possible.

This paper introduces a switched-voltage delay cell with differential inputs. It can be used as a building block for a range of analogue functions such as voltage-to-frenquency converter, A/D converter, etc. Applications incorporating the delay cell are presented. The performances are verified by simulations on PSpice.

Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

In this paper, a CMOS down-conversion double-balanced mixer is presented with the modified low voltage design technique. The frequencies of the radio frequency (RF) signal, local oscillator (LO) and intermediate frequency (IF) are 2.4 GHz, 2.3 GHz and 100 MHz, respectively. Measurement results of the proposed mixer exhibit 6.7 dB of conversion gain, -18 dBm of input 1 dB compression point (P-1 dB), -8 dBm of input-referred third-order intercept point (IIP3), and 14.7 dB single-side band (SSB) noise figure (NF) while applying -8 dBm LO power and consumes 3.3 mA from 1.8 V supply voltage. It can provide 0.7 dB conversion gain when the supply voltage reduces to 1.3 V. This mixer was fabricated in a 0.35 µm 1P4M standard digital CMOS process and the die size is 1.5 1.1 mm2.

The current voltage characteristics of the ballistic metal oxide semiconductor field effect transistor (MOSFET) is reviewed. Reducing the carrier scattering by employing e.g. the intrinsic channel structure and the low temperature operation, nanometer to sub-0.1 µm size MOSFETs operation approaches the ballistic transport. The drain current is derived by analyzing the carrier behavior in the vicinity of the potential maximum in the channel. The carrier degeneracy and the predominant carrier distribution in the lowest subband around the maximum point have critical effects on the current value. A convenient approximation of the current in terms of terminal voltages is given. The current control mechanism is discussed with use of the "Injection velocity," with which carriers are injected from the source to the channel. An index to represent the ballisticity is given, and some published experimental data are analyzed. Transport of the quasi-ballistic MOSFET is discussed.

A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO2/Si interface, was fabricated and characterized. The relations between various device parameters and characteristics of memory cell were investigated by using SPICE simulation. It was found from the simulation results that the memory window significantly changed by the device parameters, which means that the operation voltage of the memory cell can be well controlled by these parameters. The fabricated cell is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO2/Si with the area ratio of the MOS capacitor (SO) to the ferroelectric capacitor (SF) of 6 or 10. Nonvolatile memory operation was confirmed, and the obtained memory window coincided with the simulated results qualitatively. Furthermore, the current on/off ratio in the read-out operation was larger than 3-order-of magnitude and the data retention time was longer than 6 104 seconds. It was also predicted that low voltage operation was possible if the device parameters were optimized.

A new CMOS DC voltage doubler with nonoverlapping switching control is proposed, in order to eliminate the dynamic current loss during switching as well as the threshold voltage drop of the serial switches. The simulated results at 1.5 V show that the maximum power efficiency is improved with about 30%, whereas the efficiency in the low output current region is larger than 5 times compared to the conventional voltage doublers. This proposed CMOS DC voltage doubler can be used as a VPP generator of low voltage DRAM's.

EL (Electroluminescent) displays have been applied to automobiles, as their images are very clear and bright. High voltage, high integration and low power dissipation ICs are needed to drive these devices. To meet this, high voltage CMOS ICs using SOI (Silicon On Insulator) substrates are chosen as the driving devices. In this paper, an isolation structure between the output CMOS devices, of high density and high voltage is proposed. Conventional trench dielectric isolation shows degradation of a break down voltage with short distance from trench to source. In this work, the authors make clear the electric field distribution near the isolation, and offer a novel structure of "Field-plate Trench Isolation," which enables to relax the electric field on the silicon surface by shifting a part of electric field into surface oxide. Finally, operation of high voltage and high density, a 200-volt and 32-channel, EL display driver for automotive display panel is confirmed.

Voltage follower is one of the most useful building blocks in analog circuits. This paper proposes a voltage follower composed of a complementary pair of p-channel MOS(PMOS) and n-channel MOS (NMOS) differential amplifiers which operates under low power supply. The proposed circuit has a rail-to-rail dynamic range by combining complementary differential amplifiers.

A low-voltage 6-GHz-band monolithic LC-tank VCO has been fabricated using 0.2-µm CMOS/SIMOX process technology. The VCO features a tuning-range switching technique to achieve a wide tuning range. The output frequency range is between 5.71 and 6.21 GHz owing to the tuning-range switch. With the tuning-range switch on or off, the phase noise is about -100 dBc/Hz at 1-MHz offset and about -120 dBc/Hz at 10-MHz offset frequency at the supply voltage of 2 V.

This paper describes 1.0 V operation power performance of a double doped AlGaAs/InGaAs/AlGaAs heterojunction FET for personal digital cellular phones. The developed FET with a multilayer cap consisting of a highly Si-doped GaAs, an undoped GaAs and a highly Si-doped AlGaAs exhibited an on-resistance of 1.3 Ωmm and a maximum drain current of 620 mA/mm. A 28 mm gate-width device, operating with a drain bias voltage of 1.0 V, demonstrated an output power of 1.0 W, a power-added efficiency of 59% and an associated gain of 13.7 dB at an adjacent channel leakage power at 50 kHz off-center frequency of -48 dBc with a 950 MHz π/4-shifted quadrature phase shift keying signal.

This paper reviews analog-circuit researches in the 1990's especially from an academic-side point of view with the aim of pursuing what becomes important in the 21st century. To achieve this aim a large number of articles are surveyed and more than 200 are listed in References.

The subject of this study is to propose a new structure that can realize simultaneously high breakdown voltage and high packing density for both Nch low side switch and Pch high side switch in 200 V class rating. As the conventional techniques for the electric field relaxation, the structure of field plate, field ring and RESURF are well known, but these techniques are inadequate for the high packing density because they are the techniques in surface region. In order to conquer this subject, it is necessary to relax the electric field in the deep region. The electric field relaxation was investigated by device simulation. In the Nch low side switch the electric field is relaxed by buried oxide film in SOI structure. However, electric field relaxation cannot be realized only by adapting the SOI structure for Pch high side switch. Then we tried to insert an intrinsic layer between P-drift layer and the buried oxide film in order to spread the depletion layer in the deep region. This spread depletion layer by intrinsic layer and the depletion layer by field plate connect vertically, and the dosage of the ion implantation for drift layer can be set to two times higher than the case without intrinsic layer. As the results, it was revealed that the SOI structure with intrinsic layer is effective to achieve this subject. Furthermore, by fabricating both Nch low side switch and Pch high side switch on intrinsic SOI substrate, breakdown voltage more than 250 V were achieved.

A 3.3 V CMOS PLL (Phase Locked loop) with a self-feedback VCO (Voltage Controlled Oscillator) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of VCO with a new delay cell. The proposed VCO with a self-feedback path operates at a wide frequency range of 30 MHz-1 GHz with a good linearity. The DC-DC Voltage Up/Down Converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 µm n-well CMOS process. The simulation results illustrate a locking time of 2.6 µsec at 1 GHz, lock in range of 100 MHz-1 GHz, and a power dissipation of 112 mW.

This paper describes a Variable Threshold-voltage CMOS technology (VTCMOS) which controls the threshold voltage (VTH) by means of substrate bias control. Circuit techniques to combine a switch circuit for an active mode and a pump circuit for a standby mode are presented. Design considerations, such as latch-up immunity and upper limit of reverse substrate bias, are discussed. Experimental results obtained from chips fabricated in a 0.3 µm VTCMOS technology are reported. VTH controllability including temperature dependence and influence on short channel effect, power penalty caused by the control circuit, substrate current dependence at low VTH, and substrate noise influence on circuit performance are investigated. A scaling theory is also presented for use in the discussion of future possibilities and problems involved in this technology.

Random modulation refers to the changing of the MOSFET threshold voltage cell by cell. This paper claims it is essential in sub-2-V CMOS design because it reduces the sub-threshold leakage current even in the active and sleep modes as well as in the stand-by mode. We found that a gradated modulation scheme, which gradually changes the ratio of low- Vth cells according to the path-delay, is the best approach. To achieve the minimal leakage current, the way of determining the optimum pair of threshold voltages is also described. Experimental results for microprocessor show that gradated modulation reduces sub-threshold leakage current by 75% to 90% compared to conventional single-low-threshold voltage design without degrading the performance of the circuits.

An 1 V, 50 MHz, 16-bit DSP core was developed using a 0.25-µm Dual Vt library, SRAM, and Mask ROM tailored for 1 V operation. The core speed was 41% enhanced using an alternate MAC and 2-stage execution pipeline. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. An new long wire delay estimation method enhanced the synthesis. The measured power consumption at 0.9 V was 8.7 mW, which was 40% less than the power of the normal library's at 1.3 V, when the PSI-CELP CODEC firmware was run at 40 MHz.

Voltage holding property of liquid crystal (LC) cell for long period was investigated and the experimantal results were analyzed using a microscopic model considered the movement of ions in LC layer. The time dependent voltage decay curve observed in the experiment, which is not driven by the analysis with the conventional equivalent circuit comprised of the capacitance and the resistance, can be well explained by the microscopic model.