Reliability is an important figure of merit of the system and it must be satisfied in safety-critical applications. This paper considers parallel applications on heterogeneous embedded systems and proposes a two-phase algorithm framework to minimize energy consumption for satisfying applications’ reliability requirement. The first phase is for initial assignment and the second phase is for either satisfying the reliability requirement or improving energy efficiency. Specifically, when the application’s reliability requirement cannot be achieved via the initial assignment, an algorithm for enhancing the reliability of tasks is designed to satisfy the application’s reliability requirement. Considering that the reliability of initial assignment may exceed the application’s reliability requirement, an algorithm for reducing the execution frequency of tasks is designed to improve energy efficiency. The proposed algorithms are compared with existing algorithms by using real parallel applications. Experimental results demonstrate that the proposed algorithms consume less energy while satisfying the application’s reliability requirements.

Extremely low-voltage charge pump (ELV-CP) and its dedicated multi-stage driver (MS-DRV) for sub-60-mV thermoelectric energy harvesting are proposed. The proposed MS-DRV utilizes the output voltages of each ELV-CP to efficiently boost the control clock signals. The boosted clock signals are used as switching signals for each ELV-CP and MS-DRV to turn switch transistors on and off. Moreover, reset transistors are added to the MS-DRV to ensure an adequate non-overlapping period between switching signals. Measurement results demonstrated that the proposed MS-DRV can generate boosted clock signals of 350 mV from input voltage of 60 mV. The ELV-CP can boost the input voltage of 100 mV with 10.7% peak efficiency. The proposed ELV-CP and MS-DRV can boost the low input voltage of 56 mV.

This paper describes a programmable differential bandgap reference (PD-BGR) for ultra-low-power IoT (Internet-of-Things) edge node devices. The PD-BGR consists of a current generator (CG) and differential voltage generator (DVG). The CG is based on a bandgap reference (BGR) and generates an operating current and a voltage, while the DVG generates another voltage from the current. A differential voltage reference can be obtained by taking the voltage difference from the voltages. The PD-BGR can produce a programmable differential output voltage by changing the multipliers of MOSFETs in a differential pair and resistance with digital codes. Simulation results showed that the proposed PD-BGR can generate 25- to 200-mV reference voltages with a 25-mV step within a ±0.7% temperature inaccuracy in a temperature range from -20 to 100°C. A Monte Carlo simulation showed that the coefficient of the variation in the reference was within 1.1%. Measurement results demonstrated that our prototype chips can generate stable programmable differential output voltages, almost the same results as those of the simulation. The average power consumption was only 88.4 nW, with a voltage error of -4/+3 mV with 5 samples.

This letter studies the secrecy outage probability (SOP) and the secrecy diversity order of Alamouti STBC with decision feedback (DF) detection over the time-selective fading channels. For given temporal correlations, we have derived the exact SOPs and their asymptotic approximations for all possible combinations of detection schemes including joint maximum likehood (JML), zero-forcing (ZF), and DF at Bob and Eve. We reveal that the SOP is mainly influenced by the detection scheme of the legitimate receiver rather than eavesdropper and the achievable secrecy diversity order converges to two and one for JML only at Bob (i.e., JML-JML/ZF/DF) and for the other cases (i.e., ZF-JML/ZF/DF, DF-JML/ZF/DF), respectively. Here, p-q combination pair indicates that Bob and Eve adopt the detection method p ∈ {JML, ZF, DF} and q ∈ {JML, ZF, DF}, respectively.

The automatic defect detection for fabric images is an essential mission in textile industry. However, there are some inherent difficulties in the detection of fabric images, such as complexity of the background and the highly uneven scales of defects. Moreover, the trade-off between accuracy and speed should be considered in real applications. To address these problems, we propose a novel model based on YOLOv4 to detect defects in fabric images, called Feature Augmentation YOLO (FA-YOLO). In terms of network structure, FA-YOLO adds an additional detection head to improve the detection ability of small defects and builds a powerful Neck structure to enhance feature fusion. First, to reduce information loss during feature fusion, we perform the residual feature augmentation (RFA) on the features after dimensionality reduction by using 1×1 convolution. Afterward, the attention module (SimAM) is embedded into the locations with rich features to improve the adaptation ability to complex backgrounds. Adaptive spatial feature fusion (ASFF) is also applied to output of the Neck to filter inconsistencies across layers. Finally, the cross-stage partial (CSP) structure is introduced for optimization. Experimental results based on three real industrial datasets, including Tianchi fabric dataset (72.5% mAP), ZJU-Leaper fabric dataset (0.714 of average F1-score) and NEU-DET steel dataset (77.2% mAP), demonstrate the proposed FA-YOLO achieves competitive results compared to other state-of-the-art (SoTA) methods.

To reduce the common mode voltage (CMV), suppress the CMV spikes, and improve the steady-state performance, a simplified reactive torque model predictive control (RT-MPC) for induction motors (IMs) is proposed. The proposed prediction model can effectively reduce the complexity of the control algorithm with the direct torque control (DTC) based voltage vector (VV) preselection approach. In addition, the proposed CMV suppression strategy can restrict the CMV within ±Vdc/6, and does not require the exclusion of non-adjacent non-opposite VVs, thus resulting in the system showing good steady-state performance. The effectiveness of the proposed design has been tested and verified by the practical experiment. The proposed algorithm can reduce the execution time by an average of 26.33% compared to the major competitors.

The influence of the gate voltage or base pair ratio modulation on the λ-DNA FET performance was examined. The result of the gate voltage modulation indicated that the captured electrons in the guanine base of the λ-DNA molecules greatly influenced the Id-Vd characteristics, and that of the base pair ratio modulation indicated that the tendency of the conductivity was partly clarified by considering the activation energy of holes and electrons and the length and numbers of the serial AT or GC sequences over which the holes or electrons jumped. In addition, the influence of the dimensionality of the DNA molecule on the conductivity was discussed theoretically.

Recent embedded systems require both traditional machinery control and information processing, such as network and GUI handling. A dual-OS platform consolidates a real-time OS (RTOS) and general-purpose OS (GPOS) to realize efficient software development on one physical processor. Although the dual-OS platform attracts increasing attention, it often suffers from energy inefficiency in the GPOS for guaranteeing real-time responses of the RTOS. This paper proposes an energy minimization method called DVFS virtualization, which allows running multiple DVFS policies dedicated to the RTOS and GPOS, respectively. The experimental evaluation using a commercial microcontroller showed that the proposed hardware could change the supply voltage within 500 ns and reduce the energy consumption of typical applications by 60 % in the best case compared to conventional dual-OS platforms. Furthermore, evaluation using a commercial microprocessor achieved a 15 % energy reduction of practical open-source software at best.

An output voltage estimation and regulation system for a wireless power transfer (WPT) circuit is proposed. Since the fluctuation of a coupling condition and/or a load may vary the voltage supplied with WPT resulting in a malfunction of wireless-powered devices, the output voltage regulation is needed. If the output voltage is regulated by a voltage regulator in a secondary side of the WPT circuit with fixed input power, the voltage regulator wastes the power to regulate the voltage. Therefore the output voltage regulation using a primary-side control, which adjusts the input power depending on the load and/or the coupling condition, is a promising approach for efficient regulation. In addition, it is desirable to eliminate feedback loop from the secondary side to the primary side from the viewpoint of reducing power dissipation and system complexity. The proposed system can estimate and regulate the output voltage independent of both the coupling and the load variation without the feedback loop. An usable range of the coupling coefficient and the load is improved compared to previous works. The validity of the proposed system is confirmed by the SPICE simulator.

Precision microwave measurement systems require highly stable oscillators with both excellent long-term and short-term stability. Compared to components used in laboratory instruments, dielectric resonator oscillators (DRO) offer low phase noise with greatly reduced mechanical complexity. To further enhance performance, phase-locked loop (PLL) stabilization can be used to eliminate drift and provide precise frequency control. In this work, the design of a low-cost DRO concept is presented and its performance is evaluated through simulations and measurements. An open-loop phase noise of -107.2 dBc/Hz at 10 kHz offset frequency and 12.8 GHz output frequency is demonstrated. Drift and phase noise are reduced by a PLL, so that a very low jitter of under 29.6 fs is achieved over the entire operating bandwidth.

We present an effective system for integrating generative zero-shot classification modules into a YOLO-like dense detector to detect novel objects. Most double-stage-based novel object detection methods are achieved by refining the classification output branch but cannot be applied to a dense detector. Our system utilizes two paths to inject knowledge of novel objects into a dense detector. One involves injecting the class confidence for novel classes from a classifier trained on data synthesized via a dual-step generator. This generator learns a mapping function between two feature spaces, resulting in better classification performance. The second path involves re-training the detector head with feature maps synthesized on different intensity levels. This approach significantly increases the predicted objectness for novel objects, which is a major challenge for a dense detector. We also introduce a stop-and-reload mechanism during re-training for optimizing across head layers to better learn synthesized features. Our method relaxes the constraint on the detector head architecture in the previous method and has markedly enhanced performance on the MSCOCO dataset.

A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).

Message franking is introduced by Facebook in end-to-end encrypted messaging services. It allows to produce verifiable reports of malicious messages by including cryptographic proofs, called reporting tags, generated by Facebook. Recently, Grubbs et al. (CRYPTO'17) proceeded with the formal study of message franking and introduced committing authenticated encryption with associated data (CAEAD) as a core primitive for obtaining message franking. In this work, we aim to enhance the security of message franking and introduce forward security and updates of reporting tags for message franking. Forward security guarantees the security associated with the past keys even if the current keys are exposed and updates of reporting tags allow for reporting malicious messages after keys are updated. To this end, we firstly propose the notion of key-evolving message franking with updatable reporting tags including additional key and reporting tag update algorithms. Then, we formalize five security requirements: confidentiality, ciphertext integrity, unforgeability, receiver binding, and sender binding. Finally, we show a construction of forward secure message franking with updatable reporting tags based on CAEAD, forward secure pseudorandom generator, and updatable message authentication code.

We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1V were 0.470 and 0.1923V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively. At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37V, whereas it decreased to 0.22V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05V when the Vt variability (=-6σ) was large, but the dvlp SRAM lowered it to 0.41V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957µW at VDD=1.0V, which was 9.46% of PST of the conv SRAM (10.12µW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

In this paper, a novel reconfigurable intelligent surface (RIS)-aided full-duplex (FD) cooperative non-orthogonal multiple access (CNOMA) network is investigated over Nakagami-m fading channels, where two RISs are employed to help the communication of paired users. To evaluate the potential benefits of our proposed scheme, we first derive the closed-form expressions of the outage probability. Then, we derive users' diversity orders according to the asymptotic approximation at high signal-to-noise-ratio (SNR). Simulation results validate our analysis and reveal that users' diversity orders are affected by their channel fading parameters, the self-interference of FD, and the number of RIS elements.

This paper introduces a deep reinforcement learning approach to solve the virtual network function scheduling problem in dynamic scenarios. We formulate an integer linear programming model for the problem in static scenarios. In dynamic scenarios, we define the state, action, and reward to form the learning approach. The learning agents are applied with the asynchronous advantage actor-critic algorithm. We assign a master agent and several worker agents to each network function virtualization node in the problem. The worker agents work in parallel to help the master agent make decision. We compare the introduced approach with existing approaches by applying them in simulated environments. The existing approaches include three greedy approaches, a simulated annealing approach, and an integer linear programming approach. The numerical results show that the introduced deep reinforcement learning approach improves the performance by 6-27% in our examined cases.

Reconfigurable intelligent surface (RIS) has the capability of boosting system performance by manipulating the wireless propagation environment. This paper investigates a downlink RIS-aided non-orthogonal multiple access (NOMA) system, where a RIS is deployed to enhance physical-layer security (PLS) in the presence of an eavesdropper. In order to improve the main link's security, the RIS is deployed between the source and the users, in which a reflecting element separation scheme is developed to aid data transmission of both the cell-center and the cell-edge users. Additionally, the closed-form expressions of secrecy outage probability (SOP) are derived for the proposed RIS-aided NOMA scheme. To obtain more deep insights on the derived results, the asymptotic performance of the derived SOP is analyzed. Moreover, the secrecy diversity order is derived according to the asymptotic approximation in the high signal-to-noise ratio (SNR) and main-to-eavesdropper ratio (MER) regime. Furthermore, based on the derived results, the power allocation coefficient and number of elements are optimized to minimize the system SOP. Simulations demonstrate that the theoretical results match well with the simulation results and the SOP of the proposed scheme is clearly less than that of the conventional orthogonal multiple access (OMA) scheme obviously.

This paper refers to the optimal voltage pair, which minimizes the energy consumption of LSI circuits under a target delay constraint, as a Minimum Energy Point (MEP). This paper proposes an approximation-based implementation method for an MEP tracking system over a wide voltage region. This paper focuses on the MEP characteristics that the energy loss is sufficiently small even though the voltage point changes near the MEP. For example, the energy loss is less than 5% even though the estimated MEP differs by a few tens of millivolts in comparison with the actual MEP. Therefore, the complexity for determining the MEP is relaxed by approximating complex operations such as the logarithmic or the exponential functions in the MEP tracking algorithm, which leads to hardware-/software-efficient implementation. When the MEP tracking algorithm is implemented in software, the MEP estimation time is reduced from 1ms to 13µs by the proposed approximation. When implemented in hardware, the proposed method can reduce the area of an MEP estimation circuit to a quarter. Measurement results of a 32-bit RISC-V processor fabricated in a 65-nm SOTB process technology show that the energy loss introduced by the proposed approximation is less than 2% in comparison with the MEP operation. Furthermore, we show that the MEP can be tracked within about 45 microseconds by the proposed MEP tracking system.

Quadrature voltage-controlled oscillators (VCOs) with current-weight-average and voltage-weight-average phase-adjusting architectures are studied. The phase adjusting equalizes the oscillation frequency to the LC-resonant frequency. The merits of the equalization are explained by using Leeson's phase noise equation and the impulse sensitivity function (ISF). Quadrature VCOs with the phase-adjusting architectures are fabricated using 180-nm TSMC CMOS and show low-phase-noise performances compared to a conventional differential VCO. The ISF analysis and small-signal analysis also show that the drawbacks of the current-weight-average phase-adjusting and voltage-weight-average phase-adjusting architectures are current-source noise effect and large additional capacitance, respectively. A voltage-average-adjusting circuit with a source follower at its input alleviates the capacitance increase.

Intelligent reconfigurable surfaces (IRS) have attracted much attention from both industry and academia due to their performance improving capability and low complexity for 6G wireless communication systems. In this letter, we introduce an IRS-assisted space-time line code (STLC) technique. The STLC was introduced as a promising technique to acquire the optimal diversity gain in 1×2 single-input multiple-output (SIMO) channel without channel state information at receiver (CSIR). Using the cosine similarity theorem, we propose a novel phase-steering technique for the proposed IRS-assisted STLC technique. We also mathematically characterize the proposed IRS-assisted STLC technique in terms of outage probability and bit-error rate (BER). Based on computer simulations, it is shown that the results of analysis shows well match with the computer simulation results for various communication scenarios.