A 150 GHz fundamental oscillator employing an inter-stage matching network based on a transmission line is presented in this letter. The proposed oscillator consists of a two-stage common-emitter amplifier loop, whose inter-stage connections are optimized to meet the oscillation condition. The oscillator is designed in a 130-nm SiGe BiCMOS process that offers fT and fMAX of 350 GHz and 450 GHz. According to simulation results, an output power of 3.17 dBm is achieved at 147.6 GHz with phase noise of -115 dBc/Hz at 10 MHz offset and figure-of-merit (FoM) of -180 dBc/Hz.

Wide deployment of artificial intelligence (AI) is inducing exponentially growing energy consumption. Traditional digital platforms are becoming difficult to fulfill such ever-growing demands on energy efficiency as well as computing latency, which necessitates the development of high efficiency analog hardware platforms for AI. Recently, optical and electrooptic hybrid computing is reactivated as a promising analog hardware alternative because it can accelerate the information processing in an energy-efficient way. Integrated photonic circuits offer such an analog hardware solution for implementing photonic AI and machine learning. For this purpose, we proposed a photonic analog of support vector machine and experimentally demonstrated low-latency and low-energy classification computing, which evidences the latency and energy advantages of optical analog computing over traditional digital computing. We also proposed an electrooptic Hopfield network for classifying and recognizing time-series data. This paper will review our work on implementing classification computing and Hopfield network by leveraging silicon photonic circuits.

Quadrature phase-shift keying (QPSK) and 16-quadrature amplitude modulation (16QAM) formats are deployed in inter-data center networks where high transmission capacity and spectral efficiency are required. However, in intra-data center networks, a four-level pulse amplitude modulation (PAM4) format is deployed to satisfy the requirements for a simple and low-cost transceiver configuration. For the seamless and effective connection of such heterogeneous networks without an optical-electrical-optical conversion, an all-optical modulation format conversion technique is required. In this paper, we propose all-optical PAM4 to QPSK and 16QAM modulation format conversions using silicon-rich nitride waveguides. The successful conversions from 50-Gbps-class PAM4 signals to 50-Gbps-class QPSK and 100-Gbps-class 16QAM signals are demonstrated via numerical simulations.

We propose a novel silicon diplexer integrated with filters for frequency-division multiplexing in the 300-GHz band. The diplexer consists of a directional coupler formed of unclad silicon wires, a photonic bandgap-based low-pass filter, and a high-pass filter based on frequency-dependent bending loss. These integrated filters are capable of suppressing crosstalk and providing >15dB isolation over 40GHz, which is highly beneficial for terahertz-range wireless communications applications. We have used this diplexer in a simultaneous error-free wireless transmission of 300-GHz and 335-GHz channels at the aggregate data rate of 36Gbit/s.

We evaluated the energy efficiency per 1-bit transmission of an optical light source on InP substrate to achieve optical interconnection. A semiconductor optical amplifier (SOA) assisted extended reach EADFB laser (AXEL) was utilized as the optical light source to enhance the energy efficiency compared to the conventional electro-absorption modulator integrated with a DFB laser (EML). The AXEL has frequency bandwidth extendibility for operation of over 100Gbit/s, which is difficult when using a vertical cavity surface emitting laser (VCSEL) without an equalizer. By designing the AXEL for low power consumption, we were able to achieve 64-Gbit/s, 1.0pJ/bit and 128-Gbit/s, 1.5pJ/bit operation at 50°C with the transmitter dispersion and eye closure quaternary of 1.1dB.

Indoor free space optical (FSO) communication technology that provides high-speed connectivity to edge users is expected to be introduced in the near future mobile communication system, where the silicon photonics solid-state beam scanning device is a promising tool because of its low cost, long-term reliability, and other beneficial properties. However, the current two-dimensional beam scanning devices using grating coupler arrays have difficulty in increasing the transmission capacity because of bandwidth regulation. To solve the problem, we have introduced a broadband surface optical coupler, “elephant coupler,” which has great potential for combining wavelength and spatial division multiplexing technologies into the beam scanning device, as an alternative to grating couplers. The prototype port-selective silicon beam scanning device fabricated using a 300 mm CMOS pilot line achieved broadband optical beam emission with a 1 dB-loss bandwidth of 40 nm and demonstrated beam scanning using an imaging lens. The device has also exhibited free-space signal transmission of non-return-to-zero on-off-keying signals at 10 Gbps over a wide wavelength range of 60 nm. In this paper, we present an overview of the developed beam scanning device. Furthermore, the theoretical design guidelines for indoor mobile FSO communication are discussed.

The optical phased array (OPA) is an emerging non-mechanical device that enables high-speed beam steering by emitting precisely phase-controlled lightwaves from numerous optical antennas. In practice, however, it is challenging to drive all phase shifters on an OPA in a deterministic manner due to the inevitable fabrication-induced phase errors and crosstalk between the phase shifters. In this work, we fabricate a 16-element silicon photonic non-redundant OPA chip with integrated phase monitors and experimentally demonstrate accurate monitoring of the relative phases of light from each optical antenna. Under the beam steering condition, the optical phase retrieved from the on-chip phase monitors varies linearly with the steering angle, as theoretically expected.

Recent years have seen a decline in the art of analog IC design even though analog interface and analog signal processing remain just as essential as ever. While there are many contributing factors, four specific pressures which contribute the most to the loss of creativity and innovation within analog practice are examined: process evolution, risk aversion, digitally assisted analog, and corporate culture. Despite the potency of these forces, none are found to be insurmountable obstacles to reinvigorating the industry. A more creative future is within our reach.

Reducing on-chip microwave crosstalk is crucial for semiconductor spin qubit integration. Toward crosstalk reduction and qubit integration, we investigate on-chip microwave crosstalk for gate electrode pad designs with (i) etched trenches between contact pads or (ii) contact pads with reduced sizes. We conclude that the design with feature (ii) is advantageous for high-density integration of semiconductor qubits with small crosstalk (below -25 dB at 6 GHz), favoring the introduction of flip-chip bonding.

We have proposed and demonstrated a device fabrication process of physically defined quantum dots utilizing electron beam lithography employing a negative-tone resist toward high-density integration of silicon quantum bits (qubits). The electrical characterization at 3.8K exhibited so-called Coulomb diamonds, which indicates successful device operation as single-electron transistors. The proposed device fabrication process will be useful due to its high compatibility with the large-scale integration process.

In a convex grid drawing of a plane graph, all edges are drawn as straight-line segments without any edge-intersection, all vertices are put on grid points and all facial cycles are drawn as convex polygons. A plane graph G has a convex drawing if and only if G is internally triconnected, and an internally triconnected plane graph G has a convex grid drawing on an (n-1) × (n-1) grid if either G is triconnected or the triconnected component decomposition tree T(G) of G has two or three leaves, where n is the number of vertices in G. An internally triconnected plane graph G has a convex grid drawing on a 2n × 2n grid if T(G) has exactly four leaves. Furthermore, an internally triconnected plane graph G has a convex grid drawing on a 20n × 16n grid if T(G) has exactly five leaves. In this paper, we show that an internally triconnected plane graph G has a convex grid drawing on a 10n × 5n grid if T(G) has exactly five leaves. We also present a linear-time algorithm to find such a drawing.

We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1V were 0.470 and 0.1923V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively. At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37V, whereas it decreased to 0.22V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05V when the Vt variability (=-6σ) was large, but the dvlp SRAM lowered it to 0.41V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957µW at VDD=1.0V, which was 9.46% of PST of the conv SRAM (10.12µW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

This paper describes an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface and proposes two countermeasures. This work analyzes the crosstalk among seven stacked chips using a 3D electromagnetic (EM) simulator. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress these crosstalks, this paper proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of these coils improves area efficiency by a factor of 4 in simulation. The proposed methods enable an area-efficient inductive coupling interface for high-bandwidth stacked memory.

We have designed a near-infrared wavelength Si/CaF2 DFB quantum cascade laser and investigated the possibility of single-mode laser oscillation by analysis of the propagation mode, gain, scattering time of Si quantum well, and threshold current density. As the waveguide and resonator, a slab-type waveguide structure with a Si/CaF2 active layer sandwiched by SiO2 on a Si (111) substrate and a grating structure in an n-Si conducting layer were assumed. From the results of optical propagation mode analysis, by assuming a λ/4-shifted bragg waveguide structure, it was found that the single vertical and horizontal TM mode propagation is possible at the designed wavelength of 1.70µm. In addition, a design of the active layer is proposed and its current injection capability is roughly estimated to be 25.1kA/cm2, which is larger than required threshold current density of 1.4kA/cm2 calculated by combining analysis results of the scattering time, population inversion, gain of quantum cascade lasers, and coupling theory of a Bragg waveguide. The results strongly indicate the possibility of single-mode laser oscillation.

SiC-MOSFETs are being increasingly implemented in power electronics systems as low-loss, fast switching devices. Despite the advantages of an SiC-MOSFET, its large dv/dt or di/dt has fear of electromagnetic interference (EMI) noise. This paper proposes and demonstrates a simple and robust gate driver that can suppress ringing oscillation and surge voltage induced by the turn-off of the SiC-MOSFET body diode. The proposed gate driver utilizes the channel leakage current methodology (CLC) to enhance the damping effect by elevating the gate-source voltage (VGS) and inducing the channel leakage current in the device. The gate driver can self-adjust the timing of initiating CLC operation, which avoids an increase in switching loss. Additionally, the output voltage of the VGS elevation circuit does not need to be actively controlled in accordance with the operating conditions. Thus, the circuit topology is simple, and ringing oscillation can be easily attenuated with fixed circuit parameters regardless of operating conditions, minimizing the increase in switching loss. The effectiveness and versatility of proposed gate driver were experimentally validated for a wide range of operating conditions by double and single pulse switching tests.

In this research, the effect of Ar/N2-plasma sputtering gas pressure on the LaBxNy tunnel and block layer was investigated for pentacene-based floating-gate memory with an amorphous rubrene (α-rubrene) passivation layer. The influence of α-rubrene passivation layer for memory characteristic was examined. The pentacene-based metal/insulator/metal/insulator/semiconductor (MIMIS) diode and organic field-effect transistor (OFET) were fabricated utilizing N-doped LaB6 metal layer and LaBxNy insulator with α-rubrene passivation layer at annealing temperature of 200°C. In the case of MIMIS diode, the leakage current density and the equivalent oxide thickness (EOT) were decreased from 1.2×10-2 A/cm2 to 1.1×10-7 A/cm2 and 3.5 nm to 3.1 nm, respectively, by decreasing the sputtering gas pressure from 0.47 Pa to 0.19 Pa. In the case of floating-gate type OFET with α-rubrene passivation layer, the larger memory window of 0.68 V was obtained with saturation mobility of 2.2×10-2 cm2/(V·s) and subthreshold swing of 199 mV/dec compared to the device without α-rubrene passivation layer.

In a convex grid drawing of a plane graph, all edges are drawn as straight-line segments without any edge-intersection, all vertices are put on grid points and all facial cycles are drawn as convex polygons. A plane graph G has a convex drawing if and only if G is internally triconnected, and an internally triconnected plane graph G has a convex grid drawing on an (n-1)×(n-1) grid if either G is triconnected or the triconnected component decomposition tree T(G) of G has two or three leaves, where n is the number of vertices in G. An internally triconnected plane graph G has a convex grid drawing on a 2n×2n grid if T(G) has exactly four leaves. Furthermore, an internally triconnected plane graph G has a convex grid drawing on a 6n×n2 grid if T(G) has exactly five leaves. In this paper, we show that an internally triconnected plane graph G has a convex grid drawing on a 20n×16n grid if T(G) has exactly five leaves. We also present an algorithm to find such a drawing in linear time. This is the first algorithm that finds a convex grid drawing of such a plane graph G in a grid of O(n2) size.

Copper sulfide nanoparticles were successfully prepared by laser ablation in liquid. CuS powders in deionized water were irradiated with nanosecond-pulsed laser (Nd:YAG, SHG) to prepare nanoparticles. Prepared nanoparticles were investigated by scanning electron microscopy (SEM), dynamic light scattering (DLS) and fluorospectrometer. According to the results of SEM and DLS, the primary and secondary particle size was decreased with the increase in laser fluence of laser ablation in liquid. The ratio of Cu and S of prepared nanoparticles were not changed. The absorbance of prepared copper sulfide nanoparticles in water was increased with the increase in laser fluence.

This paper summarizes our recent studies on architecture, photonic integration, system validation and networking performance analysis of a flexible low-latency interconnect optical network switch (Flex-LIONS) for datacenter and high-performance computing (HPC) applications. Flex-LIONS leverages the all-to-all wavelength routing property in arrayed waveguide grating routers (AWGRs) combined with microring resonator (MRR)-based add/drop filtering and multi-wavelength spatial switching to enable topology and bandwidth reconfigurability to adapt the interconnection to different traffic profiles. By exploiting the multiple free spectral ranges of AWGRs, it is also possible to provide reconfiguration while maintaining minimum-diameter all-to-all interconnectivity. We report experimental results on the design, fabrication, and system testing of 8×8 silicon photonic (SiPh) Flex-LIONS chips demonstrating error-free all-to-all communication and reconfiguration exploiting different free spectral ranges (FSR0 and FSR1, respectively). After reconfiguration in FSR1, the bandwidth between the selected pair of nodes is increased from 50Gb/s to 125Gb/s while an all interconnectivity at 25Gb/s is maintained using FSR0. Finally, we investigate the use of Flex-LIONS in two different networking scenarios. First, networking simulations for a 256-node datacenter inter-rack communication scenario show the potential latency and energy benefits when using Flex-LIONS for optical reconfiguration based on different traffic profiles (a legacy fat-tree architecture is used for comparison). Second, we demonstrate the benefits of leveraging two FSRs in an 8-node 64-core computing system to provide reconfiguration for the hotspot nodes while maintaining minimum-diameter all-to-all interconnectivity.

Silicon photonics technology is a promising candidate for small form factor transceivers that can be used in data-center applications. This technology has a small footprint, a low fabrication cost, and good temperature immunity. However, its main challenge is due to the high baud rate operation for optical modulators with a low power consumption. This paper investigates an all-Silicon Mach-Zehnder modulator based on the lumped-electrode optical phase shifters. These phase shifters are driven by a complementary metal oxide semiconductor (CMOS) inverter driver to achieve a low power optical transmitter. This architecture improves the power efficiency because an electrical digital-to-analog converter (DAC) and a linear driver are not required. In addition, the current only flows at the time of data transition. For this purpose, we use a PIN-diode phase shifter. These phase shifters have a large capacitance so the driving voltage can be reduced while maintaining an optical phase shift. On the other hand, this study integrates a passive resistance-capacitance (RC) equalizer with a PIN-phase shifter to expand the electro-optic (EO) bandwidth of a modulator. Therefore, the modulation efficiency and the EO bandwidth can be optimized by designing the capacitor of the RC equalizer. This paper reviews the recent progress for the high-speed operation of an all-Si PIN-RC modulator. This study introduces a metal-insulator-metal (MIM) structure for a capacitor with a passive RC equalizer to obtain a wider EO bandwidth. As a result, this investigation achieves an EO bandwidth of 35.7-37 GHz and a 70 Gbaud NRZ operation is confirmed.