We propose a neutron diffractometer system based on MgB₂ thin film detectors and an SFQ signal processor. Small dimensions of MgB₂ thin film detectors and high processing capability of the single flux quantum (SFQ) circuits enable us to handle several thousand or more detectors in a cryocooler, leading to a very compact system. In addition, the system can provide many diffraction patterns for different kinetic energies simultaneously. Kinetic energy is determined for individual neutrons by means of the time-of-flight method by using SFQ time-to-digital converters (TDCs). Digital outputs of the TDCs are multiplexed in time domain and sent to room-temperature electronics with reduced number of cables. A dual-input SFQ signal processor including TDCs and a multiplexer has been successfully demonstrated with a time resolution of 20 ns and power consumption of 400 µW. These values show high feasibility of the neutron diffraction system proposed here.

We report on the enhancement of system detection efficiency in a superconducting nanowire single-photon detector (SNSPD) by applying the optical cavity structure. The nanowire was made using 4-nm-thick NbN thin films and covered with an SiO cavity and Au mirror designed for 1300-1600 nm wavelengths. The device is mounted into fiber-coupled packages, and installed in a practical multichannel system based on GM cryocoolers. System detection efficiency depends on the absorptance of cavity structure, and reached 28% and 40% at 1550 nm and 1310 nm wavelengths, respectively. These values were considerably higher than an SNSPD without optical cavity.

Effect of an addition of a cooled step-up transformer to a flux locked loop (FLL) circuit was studied to reduce indirect rf interference to HTS-dc-SQUID. First, we demonstrated that a noise level of an HTS-dc-SQUID system using the FLL circuit with single room-temperature transformer could be easily degraded by radiation of rf electromagnetic wave to cables in the FLL circuit. It is thought that the rf radiation induced rf current in the circuit, and was transmitted to the SQUID to modulate the bias current, resulting in the increase of the noise level. To avoid the degradation due to such indirect rf interference, the cooled set-up transformer was added to the FLL circuit since it was expected that the additional transformer would work as a "step-down" transformer against the induced rf current. It was shown that the noise level of a HTS-SQUID system (SQUITEM system) operated in an electromagnetically unshielded environment could be improved to the same level as that measured in a magnetically shielded room by the additional cooled transformer and appropriate impedance matching.

AC-waveform synthesis with quantum-mechanical accuracy has been attracting many researchers, especially metrologists in national metrology institutes, not only for its scientific interest but its potential benefit to industries. We describe the current status at National Metrology Institute of Japan of development of a Josephson arbitrary waveform synthesizer based on programmable and pulse-driven Josephson junction arrays.

We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.

In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.

Although larger scale integration enhances the practicability of superconducting Josephson circuits, several technical problems begin to emerge during its progress. One of the problems is the increase of current through a ground plane (ground current). Excess ground current produces additional magnetic field and reduces operation margins of the circuits, because superconducting Josephson devices are very sensitive to magnetic field. In this paper, we evaluate current distribution in a superconducting ground plane by means of both experiments and numerical calculation. We also verify two methods for suppressing the ground current. One is a slot structure in the ground plane, and the other is alignment of the current-extraction point. Suppression of the ground current is quantitatively evaluated.

We describe the fabrication processes and electrical characteristics of two types of NbN junctions. One is a self-shunted NbN/NbN_x/AlN/NbN Josephson junction, which is expected to improve the density of integrated circuits; the other is an underdamped NbN/AlN_x/NbN tunnel junction with radical-nitride AlN_x barriers, which has highly controllable junction characteristics. In the former, the junction characteristics were changed from underdamped to overdamped by varying the thickness of the NbN_x layer. Overdamped junctions with a 6-nm-thick NbN_x film exhibited a characteristic voltage of V_c = 0.8 mV and a critical current density of J_c = 22 A/cm² at 4.2 K. In the junctions with radical-nitride AlN_x barriers, J_c could be controlled in the range 0.01-3 kA/cm² by varying the process conditions, and good uniformity of the junction characteristics was obtained.

This work presents a novel field emission organic light emitting diode (FEOLED), in which an inorganic phosphor thin film is replaced by an organic EL light-emitting layer in the configuration of a field emission display (FED). The field emission electrons emitted from the carbon nanotubes (CNTs) cathode of the proposed FEOLED intensify the electron density in the multi-layer organic materials of the OLED; thus, resulting a higher luminous efficiency than that of a conventional OLED. Additionally, the luminance of the proposed FEOLED can be further increased from 10,820 cd/m² to 27,393 cd/m² by raising the current density of OLED through an external electron source. A balanced quantity of electrons and holes in the OLED, which is achieved by the proposed FEOLED increases the number of excitons and attributes the enhancement of luminous efficiency of the OLED. Under the same operating current density, the proposed FEOLED exhibits a higher luminous efficiency than that of a conventional OLED.

This paper presents the loss factors in the post-wall waveguide-fed parallel-plate slot array antenna in the millimeter-wave band. At first, transmission loss is evaluated per unit length by measuring the losses of post-wall waveguides on various substrates with different thicknesses in different bands. Measured results of the frequency dependence agree with theoretical predictions using the effective conductivity and the complex permittivity obtained by the whispering gallery mode resonator method. Then the authors evaluate the antennas with various sizes at 76.5 GHz. The antenna efficiency is evaluated by taking into account the loss factors related to: the transmission loss both in the feed and the parallel plate waveguides, the aperture efficiency and the insertion loss and the reflection of the transition. Also, the loss due to the locally-perturbed currents by the slot radiation is evaluated. The sum of the losses in the prediction quantitatively agrees with the measurement.

A millimeter-wave termination which is tolerant to the resistance error of the embedded resistive film in a multi-layered LTCC substrate has been developed. The tolerance to the resistance error can be accomplished using two bifurcated strip lines overlapping with the resistive film, whose lengths are different form each other. It has been experimentally demonstrated that the proposed termination configuration is effective to enhance the tolerance to resistance error of the embedded resistive film in the LTCC substrate.

In this paper, accuracy or error in permeability measurement using a combined microstrip line-coaxial conductor method was investigated. The measurement circuit used in this study is composed of a microstrip line (MSL) circuit and a grounded metal pipe with a center conductor passing through it coaxially. A sample is placed between the metal pipe and the center conductor. We evaluated the measurement accuracy for this measurement arrangement with electromagnetic simulation for the case where there are gaps between the sample and the holder. As a result, it has been shown that the normalized errors for this method have similar gap size dependence to the conventional coaxial method, but are about 10 to 20 percent greater than the coaxial method. With a view to improving the measurement accuracy, a correction method for the error is also discussed.

We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a g_m/I_D lookup table design methodology in scaled CMOS. This methodology advantages from using g_m/I_D as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the g_m/I_D with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and g_m/I_D lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of g_m/I_D subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of g_m/I_Ds as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125 MS/s pipeline A/D converter implemented in a 0.18 µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the g_m/I_D characteristics.

A dynamic dither gain control technique for multi-level delta-sigma Digital-to-Analog Converters (DACs) using multi-stage Dynamic Element Matching (DEM) with a second order loop filter is proposed. The proposed technique provides improvement on the mismatch shaping performance through dynamic control of delta-sigma modulator dither gain. A large dither gain, which suppresses DEM operation dependency on input signal, is applied to delta-sigma modulator, when DEM loop filter output is greater than a designed reference. The design example using the proposed technique on a third order 17-level delta-sigma modulator with 3-stage cascaded DEM is shown in this paper. Simulation result with 1% analog segment mismatch shows over 10 dB improvement of THD+N performance under -50 dB amplitude input signal, compared to the case without the proposed technique.

In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within 0.5% for embedded SRAMs. The proposed method identified the root causes of product-specific failures in 150 and 65 nm technology node products.

The long-standing problem of predicting circuit performance variations without a huge number of statistical investigations is demonstrated to be solvable by a surface-potential-based MOSFET model. Direct connection of model parameters to physical device parameters reflecting process variations and the reduced number of model parameters are the enabling key model properties. It has been proven that the surface-potential-based model HiSIM2 is capable of reproducing measured I-V and its derivatives' variations with those of device/process related model parameters. When used to predict 51-stage ring oscillator frequency variation including both inter- and intra-chip variation, it reproduces measurements with shortened simulation time.

This paper proposes a modified per-survivor iterative timing recovery scheme, which exploits a new split-preamble strategy in conjunction with a per-survivor processing soft-output Viterbi algorithm (PSP-SOVA). The conventional split-preamble strategy places a preamble at the beginning of a data sector and uses it to run a phase-locked loop during acquisition to find an initial phase/frequency offset. However, the proposed scheme splits the preamble into two parts. The first part is placed at the beginning of the data sector, whereas the second part is divided into small clusters, each of which is then embedded uniformly within the data stream. This split preamble is utilized to adjust the branch metric calculation in PSP-SOVA to ensure that the survivor path occurs in a correct direction. Results indicate that the proposed scheme yields a better performance than a conventional receiver with separate timing recovery and turbo equalization, and the iterative timing recovery scheme proposed in [1],[2], especially when the timing jitter is large. In addition, we also show that the proposed scheme can automatically correct a cycle slip much more efficiently than the others.

A 1.8 V, 5 GHz low power frequency synthesizer for Wireless Sensor Networks is presented in 0.18 µm CMOS technology. A low power phase-switching prescaler is designed, and the current mode phase rotator is merged into the first divide-by-2 circuit of the prescaler to reduce power and propagation delay. An improved charge pump circuit is proposed to compensate for the dynamic effects with the charge pump. By a divide-by-2 circuit, the frequency synthesizer can provide a 2.324-2.714 GHz quadrature output frequency in 1 MHz steps with a 4 MHz reference frequency. The measured output phase noise is -110 dBc/Hz at 1-MHz offset frequency. The power consumption of the PLL is 11.2 mW at 1.8 V supply voltage.

A new kind of 3D power divider based on a half-mode substrate integrated circular cavity (HSICC) is proposed. This novel power divider can reduce the size of a power divider based on normal substrate integrated circular cavity (SICC) by nearly a half. To verify the validity of the design method, a two-way X-band HSICC power divider using low temperature co-fired ceramic (LTCC) technology is designed, fabricated and measured.