A trial definition and position of electronic packaging technology which consists of packaging process technology and packaging assembly technology is shown. Then, evaluation of packaging technology from the system engineer's point of view is discussed. In Japan, the most recent main packaging technology is SMT. But it may be only a passing point to COX. Finally a new concept on ultimate high density packaging is introduced.

This paper describes a high-speed multichip (3232 space-division) switching module for high-definition TV broadcasting and switching systems. This newly developed module employs new Si-bipolar SST switching LSIs and a multi-layer substrate with a polyimide dielectric and a fine pattern of copper conductors. This substrate contains matrix-shaped thin film registers for terminated transmission and a spiral via hole structure to increase fabrication reliability. The module has 50 ohm characteristic impedance transmission lines with a deviation of less than 2.5%. The multichip module can handle a signal speed of 1.8 Gb/s using 1 : 1 and 1 : n connections. This technology allows a dramatic reduction in module size to 1/20 of that possible with conventional surface-mounted techniques.

A high performance multichip package (MCP) which consists of a multilayer substrate (MLS) and GaAs devices has been developed for supercomputer. The MLS is 100 mm100 mm size and fabricated with polyimide dielectric layers and 7 Cu/Ni thin film conductor layers including 2 signal layers on a wafer. The signal line is 25 µm wide and has 60 µm center to center spacings, the polyimide dielectric layer is 20 µm thick, and the minimum via hole size is 40 µm square. Maximum 21 GaAs devices and 47 Si devices are mounted on the multilayer substrate. The GaAs devices are 16 memory chips and 5 logic chips and are packed in leadless chip carriers (LCCs). LCCs are attached on the substrate by In/Pb soldering technique. Si devices are 52-lead TAB (Tape Automated Bonding) chips and directly attached on the substrate. The multichip package has 408 I/Os and power dissipation is approximately 150 W. This package is immersed in perfluorocarbon liquid and cooled by forced convection. The cooling capacity is studied by varing flow rate from 2 to 10 cm/s and confirmed to be sufficient to cool this high performance package. All the devices can be operated below 70. These new packaging technologies realized system performance over 10 GFOLPS, which is the world's highest.

We developed a random number generator consisting of twenty of HEMT chips which are flip-chip-bonded to a multilayer ceramic substrate with copper conductors. The thermal expansion is closely adjusted to that of GaAs from room to liquid nitrogen temperatures. The chip size are 5.0 to 8.2 mm square. Indium solder bumps were applied for bonding. The substrate size is 120 mm square and 4 mm thick. It has 16 thick-film layers at inner substrate and 2 thin-film layers on both polished outer-surfaces. The electric properties of the module were evaluated during operation in liquid nitrogen. The module stably generated random numbers at clock cycles as short as 1.49 ns in liquid nitrogen. Tests confirmed the higher switching speed of the HEMT at 77 K and also the high performance of the packaging where the substrate was composed of both a glass and an alumina-treated-zirconia powder (GAZ). The thermal expansion is closely adjusted to GaAs by the fine controlling of the glass to alumina-treated-zirconia powder ratio. Thermal shock tests from 300 K to 77 K were performed for the specimen of GAZ, alumina and fused silica. On the each of them, GaAs chips (5050.6 mm) were flip-chip-bonded with indium solder. The failure rate of the bondings increased related to the thermal-expansion difference between GaAs and the substrates (ΔTE) from 300 K to 77 K. Experimental results also indicated that the powder-ratio controlled GAZ is the more suitable for HEMT packaging as for the reliability of its bondings.

Thin-film multichip modules fabricated by chip-on-wafer (COW) technology have been developed for high performance systems. Copper/polyimide thin-film wiring layers are fabricated on a silicon substrate. LSI chips with copper-cored solder bumps (CCSBs) are flip-chip bonded to the silicon substrate. The substrate is housed in a co-fired aluminum nitride (AlN) ceramic package to enhance thermal reliability. The electrical properties, such as the characteristic impedance and crosstalk noise, of the copper/polyimide wiring substrate were examined. Experimental results have shown that the substrate can propagate high-speed signals exceeding 100 MHz. Next, this combination of a large silicon substrate and an AlN package was investigated thermally and mechanically. The results of warping tests and thermal cycling tests show that AlN is an excellent packaging material for silicon-based multichip modules. A digital signal processing module has been developed as an example of a high-performance multichip module.

Sophisticated packging technology and up-to-date semiconductor technology are the key to increase system performance. The use of high density packaging technology such as polyimide-ceramic super substrate, ultra small outline chip carrier FTC (Flipped TAB Carrier) and higher thermal conductive LCM (Liquid Cooling Module) has mainly contributed to the system performance. These packaging technologies are based upon the basic concept of Powery・Time Product Theory and Media Delay Factor. This paper introduces above basical theory and shows the packaging technologies which have been used for the NEC's super computers.

This paper describes the innovation in single chip package design for mainframe computers coupled with major advances in "Controlled Collapse Chip Connection (C4)" technology, multilayer ceramic technology, and thin-film technology. C4 technology allows the LSI chips to be connected with high integration and high-performance. Applying C4 technology to chip-to-package and package-to-module interconnections provides a higher level of connection pads out from a small package. A new material 96.5 Sn/3.5 Ag for solder joints has been developed to facilitate reliable interconnection where thermal fatigue might have been a problem. The microstructure of a fractured surface and the estimation based on "Finite Element Method (FEM)" are correlated. New material and a process of mullite-glass has been developed to attain a thermal expansion coefficient close to that of silicon. The metallized ceramic technology for the mullite-glass can be applied to the substrate of LSI packages as well as multilayer ceramic multi-chip modules. Thin-film technology has been studied to form high-density wiring on package substrates. Using photolithography technique, it is possible to pattern pads accurately enough for connection to an LSI chip. The polyimide-Al combination can be patterned by subtractive technique using liquid etchants and sputtering. The via formation process is simplified using a photosensitive polyimide so that the fabrication process for multilayer wiring becomes suitable for mass production. Hitachi recently announced the HITAC M-880 Processor Unit which makes extensive use of these technologies. The general features of the LSI package "Micro Carrier for LSI Chip (MCC)" is also outlined.

This paper presents a new ceramic package for high-frequency MMIC modules. The package is formed from a multilayer ceramic frame whose layers are metallized over most of both sides and co-fired. The inside and outside of the frame are metallized, except around the RF and DC terminals. This new package structure can eliminate ring resonances that occur in conventional ceramic packages and can provide high I/O isolation over a wide frequency range. The RF terminal is formed from microstrip lines and a through-wall microstrip designed to have a 50-ohm impedance. The insertion loss of each RF terminal is less than 0.5 dB up to 33 GHz, with complementary I/O isolation in excess of 30 dB. The new package also provides the low input V.S.W.R. of 1.3 : 1. A 30-GHz-band MMIC module incorporating four GaAs MMIC amplifiers is demonstrated. This module's maximum gain is 19 dB, and its input V.S.W.R. is 1.5 : 1 from 30.5 to 32.5 GHz.

In the transferred bump TAB (Tape Automated Bonding) technology, the bumps are transferred on the film leads, and these bumps and the aluminum electrode of an LSI chip are gang-bonded together. This technology make possible a compact semiconductor package of low cost and high reliability. In this technology, the bump formation technology and the substrate technology for the bump formation and the bonding technology contribute to its important element technology. In this treatise, the substrate technology for the bump formation and the bump formation technology corresponding to multielectrodes transferred bump TAB package will be addressed. In addition, an application for TAB package of 100 µm pitch, 444-pin will be presented.

Electronic video cameras have recently become both small and light. A CCD module is one of the principal devices in electronic video cameras, so it has been requested to become smaller and lighter. The authors have developed a subminiature CCD module. In this subminiature CCD module, a bare CCD chip is mounted directly on an optical glass substrate, and the outer circuit is connected to the surface of the glass substrate. This work needs two important assembly techniques. One is the COG wireless bonding technique, and the other is the glass outerconnecting technique. In the COG bonding technique, gold bumps are formed on aluminum pads of a CCD chip using the ball bonding method. A thick gold film wiring pattern and indium-alloy bumps are formed on the glass substrate. The CCD chip is pressed onto the glass substrate, and is heated. The CCD chip is connected electrically to the glass substrate. The glass outerconnecting technique is that of connecting an FPC (flexible printed circuit) to the glass substrate. The authors decided to use ACF (anisotropic conductive film) connection. An ACF is an adhesive film which has anisotropic conductivity. When it is placed between the glass substrates and FPC, pressed, and heated, the wiring pattern on the glass substrate is connected selectively to the corresponding electrode on the FPC. Four kinds of ACFs were examined and one of them was selected. The optimum conditions for COG wireless bonding and ACF connection using the above selected ACFs were respectively obtained. Four kinds of reliability tests, i.e., a high temperature test, low temperature test, high temperature and high humidity test, and thermal shock test, were carried out for COG bonding and ACF connection. Both COG bonding and ACF connection passed all the four reliability tests. The authors manufactured a subminiature CCD module using these new assembly technique on trial. The manufactured subminiature CCD module was small, one-fifth in volume, and light, one-tenth in weight, compared with the conventional types.

To study a flip-chip connection technology for packaging of VLSIs operated in liquid nitrogen, solder and metallization materials were examined. Flip-chip connection models which consisted of Si and GaAs model chips and alumina substrate were made using four kinds of solders; indium (In), In-48%Sn, In-40%Pb, and Sn-37%Pb (percent symbol stands for mass percent). The fatigue lives of flip-chip solder joints were measured by thermal shock tests between liquid nitrogen and room temperatures. The wettability and dissolution between the In solder and Au, Cu, Pd, Ni, Pt, Au/Cu, Au/Pd, Au/Ni and Au/Pt metallization films were also investigated. The In and In alloy solders exhibit longer fatigue life than Sn-Pb solder, when used with GaAs chips as well as Si chips. In solder shows the longest fatigue life. The Au film has good wettability with In solder, and the Pt film is extremely resistant to dissolution into In solder. Experimental results indicate that In and In alloy solders are suitable for Si and GaAs flip-chip connections in liquid nitrogen, and that Au/Pt/Ti metallization films are suitable for use with In solder for flip-chip connections in liquid nitrogen. A random number generator was assembled with HEMT LSI chips and a multilayer ceramic circuit board, using flip-chip connection with In solder and Au/Pt/Ti metallization film. This equipment generates random numbers with a clock cycle of 1.49 ns in liquid nitrogen, and operates properly after several hundred cycles between liquid nitrogen and room temperatures.

There are several kinds of semiconductor chip bonding methods--wire bonding, TAB, and flip chip bonding--and each is used in applications in ways which utilize its individual characteristics. Wire bonding is inexpensive and imposes fewer restrictions on wiring, but when used with conventional technology, it has been difficult to narrow the bonding pitch. The authors challenged themselves to develop a 40µm pitch wire bonding technology for use in development of a 600 DPI (dots per inch) LED print head. To accomplish this, a high strength ultra fine wire with a diameter of 10 µm was developed and a suitable wire bonding technology using that wire was determined. Finally, the targeted 40 µm pitch wire bonding technology was established.

This paper presents solder paste rheology and its printability. Evaluating rheology of solder paste can help to solve problems in the fine pattern printing of solder paste. To quantify the solder paste rheology, viscosity, thixotropy index and viscosity restoration ratio were measured. For these measurements, six test samples of solder paste were prepared. These characteristics can be measured by changing shear rate of viscometer in several steps. Viscosity of solder paste lowers as shear rate increases. Low shear rate viscosity and high shear rate viscosity were calculated from viscosity and thixotropy indexes. These rheological characteristics are closely related to the printing quality. Printability of the solder pastes was evaluated by experimental procedure with a fine pitch QFP (Quad Flat Package) foot print test pattern. The Taguchi method was used in this printing experiment. Analysis of variance were performed to examine factors influencing printability. Evaluated items of printability were short deposit defect, bridge defect, line width increase ratio and rolling effect. Correlation analysis between rheological characteristics and printability of solder paste was performed. Results give a suggestive theoretical zone for good printing quality, that was figured out on the thixotropy index vs. viscosity plot. Its center point is 1800 [Poise] of viscosity and 0.6 of the thixotropy index. Evaluating rheology of solder paste is important when the printability of solder paste in fine pitch technology is concerned.

Data compaction and data expansion methods for an electron beam direct writing system EBM-130V are described. EBM-130V adopts the raster scan method using a variably shaped line beam. The system does not have an effective hierarchical structure in its data format, because it has only a single deflector. So, an extra virtual layer has been introduced into the EB data format, and an artificial hierarchical data structure is used for data compaction. The compacted data is expanded by an EB control software system. For a 4 Mbit DRAM, the data amount was about 30 MBytes (compaction rate 1/16), the data conversion time was about 12 minutes (reduction rate 1/35), and the data transfer time from the system disk to the pattern data memory was reduced to about 1/5, by using the date compaction method.

A new mode-matching method is proposed here for printed-circuit analysis, which considers the field-continuity conditions via the singular aperture field at conductor edges expanded into a finite series of known singular functions with unknown coefficients. In this sense, our approach seems to be similar with the spectral-domain method in the handling of singular functions of currents on conductor strips, but the aperture plane on which singular functions are assumed is taken along a perfectly different direction. Effectiveness of this method in numerical handling is proved by the dispersion calculations of microstrip lines with isotropic and anisotropic substrates.

The two-dimensional scattering problem of electromagnetic waves by a grating composed of two arbitrarily oriented strips in one period is analyzed by means of the formulation using the mutual field. A formulation is presented for the analysis of multiple scattering by the grating by means of the representation of the scattered field by a grating composed of one strip in one period. The Wiener-Hopf equations to be satisfied by each scattered field and the representation of scattered wave based on the solution to these equation are obtained. Since the width of the strips in the grating is finite, it is difficult to carry out rigorously the decomposition in the solution of the Wiener-Hopf equations. The characteristic of the sampling function is used for expansion of the unknown function into a series so that the Wiener-Hopf equations are reduced to a set of simultaneous equations. For evaluation of the convergence and the errors in the results, the relative error with respect to the extrapolated value and the square error for satisfaction of the boundary condition are numerically computed. From numerical comparison of the present method with other various methods, it is found that the present method provides us accurate results. Some numerical examples on the reflection coefficient are presented for the reflection and transmission gratings.