The process mapping of the ALD process of HfO₂ using HfCl₄ and H₂O is reported. A thickness uniformity better than 3% was achieved over a 300 mm-wafer at a deposition rate of 0.52 Å/cycle. Usually, H₂O purge period is set less than 10 sec to obtain reasonable throughput; however, the amounts of residual impurities (Cl, H) found to be in the order of sub%, and these impurities are piled up near the HfO₂/Si interface. In order to reduce the piled up impurities, we proposed a 2-step deposition in which purge period for initial 10-20 cycles was set to be 90 sec and that for remaining cycles was usual value of 7.5 sec. The leakage current is reduced to 1/10 by using this 2-step deposition.

Thermal stability of stacked high-κ dielectrics, especially ZrO₂, HfO₂ and ZrSiO₄ /SiO₂ layered structures, on silicon has been investigated in terms of ultrahigh vacuum (UHV), 1 Torr N₂ and helium (He) gas annealing with controlled oxygen partial pressure (P_O2) at 920. Comparison of 2 nm and 20 nm ZrO₂ films under UHV annealing revealed that the trigger of silicidation is the contact of ZrO₂, SiO and Si accompanying disappearance of interfacial SiO₂ layer due to SiO desorption. In the contact position, a small amount of SiO gas can easily change ZrO₂ to ZrSi₂. This reaction model is also applicable to the silicidation of HfO₂ and ZrSiO₄, at not only stacked high-κ film/Si substrate interface, but also at gate poly-Si/high-κ film interface. Moreover, comparison of UHV, N₂ and He annealing with controlled P_O2 revealed that the optimal P_O2 ranges in He at which the thermal stability of layered structure can be achieved are wider than those in UHV and N₂. This result suggests that He gas physically may obstruct SiO creation due to the quenching of atomic vibration at degradation-prone sites in the SiO₂ /Si interface, thus reducing probability of bond breaking process, which is the first step of silicidation.

We prepared HfO₂ films by atomic layer deposition (ALD) on three kinds of silicon substrate surfaces (chemical oxide, HF-last surface and thermal oxide), and characterized their morphologies, structures, compositions, and crystallinities by physical analysis. The results revealed that the as-deposited HfO₂ films consisted of nano-crystalline particles with a different crystalline system from that of the annealed films. The size of the nano-crystalline particles on the film on the chemical oxide was smaller than those on the other surfaces. The reason is thought to be the difference in OH concentration on the substrate surface. The predominant crystalline phases of all HfO₂ films were monoclinic after annealing. Moreover, the film prepared on the chemical oxide had the smoothest surface after annealing. However, island structures with grain boundaries developed in the films on the other surfaces.

Electron cyclotron resonance (ECR) plasma oxidation of AlN thin films was studied to form the AlON high-κ gate insulator. The leakage current was found to be decreased, and also the surface roughness was improved with the ECR plasma oxidation of AlN thin films. The leakage current was further decreased after 1000 RTA in N₂ with little increase of equivalent oxide thickness (EOT) because of the high quality interfacial layer formation.

We studied nitrogen incorporation in Al₂O₃ gate dielectrics by nitrogen plasma and examined the dependence of the electrical properties on the nitrogen incorporation. We found that the nitrogen concentration and profile in Al₂O₃ films thinner than 3 nm can be controlled by the substrate temperature and the plasma conditions. The electrical characterization showed that the plasma nitridation suppresses charges in Al₂O₃ films and prevents dopant penetration through the gate dielectric without increasing the leakage current or the interfacial trap density. We also demonstrated the improved performance of a metal-oxide-semiconductor field effect transistor by using a plasma nitrided Al₂O₃ gate dielectric. These results indicate that plasma nitridation is a promising method for improving the electrical properties of Al₂O₃ gate dielectrics.

The characteristics of HfO₂ gate stacks, which consisted of the SiN layer deposited between the HfO₂ and poly-Si gate electrode and the SiON interfacial layer were investigated. The SiN layer played important role to reduce the leakage current caused by the defect of the crystallized HfO₂. The SiN layer was also effective to achieve the prevention of the interfacial reaction, the suppression of dopant penetration. Furthermore, that stack structure indicated excellent TDDB reliability fabricated by conventional high temperature processes.

The electromagnetic scattering of a plane wave by an inhomogeneous plane whose surface impedance changes locally on the plane is treated. A boundary-value problem is formulated to describe the scattering phenomenon, in which the boundary condition depends on the surface impedance of the plane. Application of the Fourier transform derives an integral equation, which is approximately solved by the method of least-squares. From the solution of the equation, the scattered field is obtained by the inverse Fourier transform. By the use of the incomplete Lipschitz-Hankel integral for the computation of the field, numerical examples are given and the scattering phenomenon is discussed.

This paper describes the performance improvement of power amplifiers by defected ground structure (DGS). Due to the excellent capability of harmonic rejection and tuning, DGS plays a great role in improving the major nonlinear behaviors of power amplifier such as output power, harmonics, power added efficiency (PAE), and the ratio between the carrier and the third order intermodulation distortion (C/IMD3). In order to verify the improvement of performances by DGS, measured data for a power amplifier, which adopts a 30 Watts LDMOS device for the operation at 2.1-2.2 GHz, are illustrated under several operating bias currents for two cases, i.e., with and without DGS attached. The principle of the improvement is described by the simple Volterra nonlinear transfer functions with the consideration of different operating classes. The obtained improvement of the 30 Watts power amplifier, under 400 mA of I_dsQ as an example, includes the reduction in the second and third harmonics by 17 dB and 20 dB, and the increase in output power, PAE, and C/IMD3 by 1.3 Watts, 3.4%, and 4.7 dB, respectively.

This paper presents practical modeling procedure of feed patterns, bond wires, and interconnects for microwave bare-chip devices. Dedicated test structures have been designed for the process. Modeling accuracy of BJTs and diodes has been unprecedentedly improved up to 30 GHz with this procedure despite popular SPICE models were used.

The reduction of undesired electromagnetic emissions in switched power converters is a hot topic. Here, we propose a chaos based methodology to synthesize PWM-like signals for controlling the drives of induction motors. This approach reduces drastically the interference due to the drive-motor ensemble, and does not significantly alter the motor performance. The benefit is a 20 dB reduction in the peak of the emitted power density spectrum. This result is herein confirmed three times: first with an analytical approach based on approximations whose impact is progressively reduced; then by means of simulation; finally by laboratory testing of a working prototype.

A modified 0.35 µm gate-length MOSFET large-signal microwave device model, based on the widely used BSIM3 model, is presented in this report. This large-signal microwave model includes a BSIM3 model together with the passive components required to fit the device dc and microwave characteristics over a wide range of biasing points and frequency operation. In this report, we propose a methodology to improve the device microwave linearity by controlling a suitable biasing condition, which is based on the predictions of this modified CMOS large-signal model. The input IM₃ enhances more than 10 dB at a 2.4 GHz operation. Furthermore, the adjacent channel power ratio also improves 7.5 dB with proper choosing device dc bias.

A novel design of Cerebellar Model Articular Controller (CMAC) is presented in this article. The controller is designed by means of a content addressable memory (CAM) to replace a hash-coding function, which is adopted by generic CMACs to tackle memory space problem how a large space maps into a small one. With a different address mapping method from hash-coding methods, each memory location of the proposed architecture includes two tuples: One is the conceptual address stored in a CAM, and another is the weight associated with the conceptual address stored in a SRAM. The CAM, with capability of fast comparison, is used to determine if any of CAM's content is identical to current conceptual address in parallel. If no match occurs, an associated mask function is triggered to expand searching range, which is centered by current conceptual address with a radius defined by the number of maskable bits. If a location in the CAM carries the similar address, the weight (in SRAM) related to this matching location would be shared and updated by both the current conceptual address and the conceptual address in this location. Therefore, the control noises caused by hash-coding methods can be attenuated significantly in either the training or the recall phases in the proposed architecture. Furthermore, if there is no match in current search, after the mask function is executed, the new conceptual address with an initial weight value would be stored in a CAM cell sequentially indexed by an incremental pointer. Instead of storing the information by scattering it over the memory, the proposed architecture sequentially stores the information by the index of this pointer to increase the memory utilization. Simulation results, (1) one input variable and two input variables cases of function approximations, (2) a truck backer-upper control, demonstrate the plausible performance of the proposed CMAC architecture. The architecture and the design criteria for the proposed controller are also discussed.

In this paper, we describe the implementation and the test results of a Bluetooth baseband module we have developed. For small chip size, we eliminate FIFOs for data buffering between hardware functional units and data buffers for bit streaming among channel coding blocks. Furthermore, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB) interfaces; and audio CODEC are performed by dedicated hardware blocks. In addition, the bitstream data path block of the link controller constructing the baseband module has been designed by considering low power. The design of the baseband module is done using fully synthesizable Verilog HDL to enhance the portability between process technologies. A field programmable gate array (FPGA) implementation of the module was tested for functional verification and real time operation of file and bitstream transfer between PCs. The module was also fabricated in a 0.25 µm CMOS technology, the core size of which is only 2.792.80 mm².

The high performance method for analyzing the time evolution of the shielding current density in the high Tc superconductor (HTS) has been investigated. After discretized by using the finite element method and the backward Euler method, the initial-boundary-value problem of the governing equations of the shielding current density is transformed to the problem in which the nonlinear algebraic equations are solved at each time step. When the deaccelerated Newton method (DNM) is applied to the solution of the equations, a decrease in the relaxation factor will not always ensure the convergence of iterations. For this reason, the DNM is modified so that the residual norm may decrease monotonously with the iteration number. The modified method is called the adaptively deaccelerated Newton method (ADNM). Although the vector function is evaluated several times at each cycle in the ADNM, the CPU time required for the ADNM is diminished considerably as compared with that for the DNM. This result indicates that the ADNM is suitable for calculating the shielding current density. The numerical code for analyzing the shielding current density has been developed on the basis of the ADNM and, as an application of the code, the magnetic shielding performance of an axisymmetric HTS plate has been analyzed.

This letter presents a novel two-dimensional (2-D) defected ground array (DGA) for planar circuits, which has horizontal and vertical periodicities of defect structure. The defect unit cell of DGA is composed of a Sierpinski carpet structure to improve the effective inductance. Measurements show that the proposed DGA provides steeper cutoff characteristics, lower cutoff frequency, and higher slow-wave factors than the conventional periodic defected ground structure in the same occupied surface.

A new concept of changing inductance values has been proposed, where a part of meander inductor is short circuited to reduce effective line length. Microwave characteristics of the short-circuited meander inductors and the meander inductor without the short circuit have been designed and fabricated on resin circuit boards. The reduction of inductance values by 40% has been successfully realized for the microwave frequency range from 0.5 GHz to 5 GHz for both designed and measured results. Using the proposed structure, low pass filters having two different cut-off frequencies have been designed and tested. Measured cut-off frequency changed 3.0 GHz to 4.2 GHz.

A new bipolar scan waveform is proposed to increase the light emission duty factor by achieving the fast address in AC plasma display panel (AC-PDP). The new bipolar scan waveform consists of two-step scan pulse, which can separate the address discharge mode into two different discharge modes: a space charge generation mode and a wall charge accumulation mode. By adopting the new bipolar scan waveform, the light emission duty factor is increased considerably under the single scan ADS driving scheme due to the reduction of address time per single subfield.