We developed a quantitative evaluation method for luminance and color uniformity on a display screen. In this paper, we report the analysis result of a viewer perception of luminance and color uniformity. In experiments, observers subjectively evaluated Mura images which were showed on the light emitting diode (LED) backlight screen by adjusting the luminance of each LED. We measured the luminance and color distributions of the Mura images by a 2D colorimeter, then, the measured data was converted into S-CIELAB. In S-CIELAB calculations, two dimensional MTF (Modulation Transfer Function) of human eye were used in which anisotropic properties of the spatial frequency response of human vision were considered. Some indexes for a quantitative evaluation model were extracted by the image processing. The significant indexes were determined by the multiple regression analysis to quantify the degree of uniformity of the backlight screen. The luminance uniformity evaluation model and color uniformity evaluation model were derived from this analysis independently. In addition, by integrating both of these models we derived a quantitative evaluation model for luminance and color unevenness simultaneously existing on the screen.

Three methods of presenting a three-dimensional (3-D) image – a real object, a protruding stereoscopic display, and the depth-fused 3-D (DFD) display – have different tendencies for the change in perceived depth produced when the visual acuity of the dominant eye is decreased by an occlusion foil. These different tendencies are estimated from the slope and correlation coefficient of the plot of perceived depth difference versus stimuli depth difference. This estimation was derived using the same experimental system setup composed of two displays and a half mirror for all three 3-D display methods. The perceived depth difference was measured for four subjects by calipers using two fingers. The slope and correlation coefficient had almost the same tendencies as follows. The real object had the smallest decrease among the three 3-D display methods when the dominant eye's visual acuity was decreased and the protruding stereoscopic display had the largest decrease. The DFD display method had an intermediate decrease between those of the real object and protruding stereoscopic display. When the dominant eye's visual acuity was high enough, the differences among the three 3-D display methods were small. When its visual acuity was decreased, the differences increased among the three 3-D display methods and became statistically significant.

There is no clear criterion yet for evaluating wipers based on performances of wiping raindrops and visibility in forward view. In the visibility evaluation in rainy driving, it is important to examine spatial frequency and contrast of objects in forward view. Spatial frequency and contrast of image which were affected by raindrops are calculated based on them of background board which were printed stripe patterns. Variations with time of power of analysed frequency and decreased contrast are synchronized with motion of the wiper for the all experimental cases. Moreover, we executed questionnaire, and evaluated the view of the background board. These results show that the proposed methods have been validated in evaluation with wiping performance.

Microwave photoconductivity decay (µ-PCD) method was applied to evaluate the effects of chemical composition and Ar⁺ plasma induced damage on the bulk and the surface states in amorphous In-Ga-Zn-O (a-IGZO) films. It was found that the peak reflectivity signal in the photoconductivity response increased with decreasing the Ga content, and had a strong correlation with the a-IGZO transistor performances. In addition, the peak reflectivity signals obtained after various Ar⁺ plasma treatment duration were well correlated with the transistor characteristics. With Ar⁺ plasma treatment, the peak reflectivity signal decreased in accordance with degradation of transistor characteristics. The µ-PCD method was found to be a very useful tool not only to evaluate the bulk and the surface states, but also to predict the performance of a-IGZO transistors subjected to various plasma processes in the production.

A CMOS current-mode S-shape correction circuit with shape-adjustable control is proposed for suiting different LCD panel's characteristics from different manufactures. The correction shape is divided into three segments for easy curve-fitting using three lower order polynomials. Each segment could be realized by a corresponding current-mode circuit. The proposed circuit consists of several control points which are designed for tuning the correction shape. The S-shape correction circuit was fabricated using the 0.35 µm TSMC CMOS technology. The measured input dynamic range of the circuit is from 0 µA to 220 µA. The -3 dB bandwidth of the circuit is up to 262 MHz in a high input current region.

A solution-processed photosensitive passivation layer with a low dielectric constant (PPLD) has been developed for an a-Si thin film transistor. The PPLD has three highly important properties: a low leakage current, low water absorption, and high-transparency. In addition to providing passivation, the PPLD doubles as a planarization layer. The photoactive property of the PPLD is convenient for its adaption to LCD manufacturing process. A photoactive compound contained in the PPLD enables the formation of contact holes and patterns via a photolithography process. Meanwhile, the PPLD requires ITO workability and strong adhesion property on metal and glass substrates. Apart from the above features, an a-Si TFT must perform with extremely high reliability if it is to replace the conventional inorganic passivation layer (SiN_x:H). This reliability has been achieved by an a-Si TFT and LCD panel coated with the PPLD. A reliability test was conducted under a high-temperature, high-humidity (HH) condition to examine how resistant the electronic characteristics were to change. The PPLD-coated LCD panel display view showed no defects for a test duration of HH200 hours. This high reliability was presumed to be at least partly attributable to the low water absorption rate of the passivation layer and the suppression of the increase of the TFT off-leakage current by the PPLD, a passivation layer designed to be non-polar as possible. Judging from the results of these experiments, this solution-processed passivation layer seems to be a viable substitute for the conventional inorganic passivation layer. For a larger screen LCD and higher drive frequency, the problem of RC delay has been emerged. The low dielectric constant of the PPLD will suppress the RC delay of the signal and realize both a higher pixel and a higher drive frequency.

The copper nitride surface characteristics according to atmospheric pressure plasma (APP) and excimer ultraviolet (EUV) treatment were compared using XPS and AFM. As the result of XPS analysis result, in C1s, the organic material removal effect was greater for EUV treatment than for APP, and the oxygen content was found to be low. In Cu (933 eV) area, the shoulder peak of Cu compound was detected, and the reduction was greater for EUV processing than for APP. In the AFM phase image which could be analyzed using the superficial viscoelasticity, the same trend was observed. On the copper nitride surface, the weak boundary O layer is formed according to the clean processing, and such phenomenon was interpreted as a factor for lowering the affinity with polymer.

Grazing incidence X-ray diffraction experiment proved that the a- and c-axes of PMDA-ODA crystals preferentially aligned in normal and parallel directions to rubbing at surface of rubbed film, and that polymer chains of residual amorphous phase aligned in rubbing direction.

A reverse mode liquid crystal (LC) display has been investigated. A driving voltage strongly depends on a morphology which changes by reactive mesogens, photo initiators and LCs. It becomes higher when the domain size of the liquid crystal and the particle of the polymer reactive mesogen are smaller.

A numerical model of multi-layered organic light emitting diode (OLED) is presented in this paper. The current density-voltage (J-V) model for OLED was performed by using the injection-limited current and bulk-limited current. The mobility equation was based on the field dependent model, so called “Poole-Frenkel mobility model.” The accuracy of this simulation was represented by comparing to the experimental results with a variable of EML thickness of multi-layered OLED device. There are two hetero-junction models which should be dealt with in the simulation. The Langevin recombination rate of electron and hole is also calculated through the device simulation.

The discharge properties and chemical surface stability of CeO₂ containing Sr (CeSrO) as the candidate for high-γ protective layer of noble plasma display panels (PDPs) are characterized. CeSrO films have superior chemical stability, because of the decrease in reactiveness on surface due to their fluorite structure. The discharge voltage is 50 V lower than that of MgO films for a pure discharge gas of Ne/Xe = 85/15 at 60 kPa. However the topmost surface, monolayer, of the CeSrO film relevant to the discharge property is hardly recovered from the damage by CO₂ impurity in discharge gas. We can expect that by pumping down to a sufficiently low CO₂ partial pressure (lower than 1 10^-3 Pa), PDP panels with very high efficiency are realized with CeSrO protective layer.

An equivalent network analysis for an arrangement that combines a microstrip line and coaxial conductor for the purpose of measuring permeability is discussed in this paper. The measurement circuit used consists of a coaxial conductor with a sample housed inside and a short microstrip line connected to both sides. The coaxial conductor is composed of an electrically grounded coaxial metal pipe with open ends and a center conductor. Equivalent networks for this arrangement are investigated to determine the complex permeability from the impedance of the measurement circuit. We have employed a π network composed of a resistor and an inductor connected in series, and shunt capacitors as the equivalent circuit for the measurement portion. It has been found that the measurement error ratio of less than a few percent can be obtained for most frequency ranges of 10 MHz to 500 MHz.

This paper presents a multi-band WCDMA receiver consisting of a multi-band low noise amplifier (LNA), a multi-band mixer and an inter-stage tunable notch filter. The notch filter is used to suppress Tx leakage, and 0.8–1.5 GHz (66%) of tuning range is achieved. The receiver achieves 33 and 30 dB conversion gain, 6.4 and 8 dB NF, 50 and 35.5 dBm IIP₂, and -6 and -4.7 dBm IIP₃ at 0.8 and 1.5 GHz, respectively. The power consumption is 121 mW from a 1.8-V power supply. The receiver is implemented in a 0.18-µm CMOS process.

A class-F high efficiency GaN power amplifier (PA) for dual band operation at 2.14 GHz and 2.35 GHz is proposed. A novel dual band harmonic-rejection load network, which controls the terminating impedances of the second and third harmonics, and contributes greatly to efficiency improvement of PA, is described. In addition, a matching network which guarantees the high efficiency and gain of PA for the desired dual bands is designed. The proposed load network has the harmonic rejection of more than 24 dB which is sufficient for rejecting harmonics, and an insertion loss of less than 0.11 dB. The dual band matching network for the maximum output power results in the measured highest output power for each operating frequency. The fabricated class-F GaN PA has 43 dBm-65.4% and 43 dBm-63.9% of output power - efficiency at the desired dual frequencies.

This paper introduces balanced switching schemes to compensate linear and quadratic gradient errors, in the unary current source array of a current-steering digital-to-analog converter (DAC). A novel algorithm is proposed to avoid the accumulation of gradient errors, yielding much less integral nonlinearities (INLs) than conventional switching schemes. Switching scheme examples with different number of current cells are also exhibited in this paper, including symmetric arrays and non-symmetric arrays in round and square outlines. (a) For symmetric arrays where each cell is divided into two parallel concentric ones, the simulated INL of the proposed round/square switching scheme is less than 25%/40% of conventional switching schemes, respectively. Such improvement is achieved by the cancelation of linear errors and the reduction of accumulated quadratic errors to near the absolute lower bound, using the proposed balanced algorithm. (b) For non-symmetric arrays, i.e. arrays where cells are not divided into parallel ones, linear errors cannot be canceled, and the accumulated INL varies with different quadratic error distribution centers. In this case, the proposed algorithm strictly controls the accumulation of quadratic gradient errors, and different from the algorithm in symmetric arrays, linear errors are also strictly controlled in two orthogonal directions simultaneously. Therefore, the INLs of the proposed non-symmetric switching schemes are less than 64% of conventional switching schemes.

This paper proposes a third-order low-distortion delta-sigma modulator (DSM). The third-order noise shaping is achieved by a single opamp (excluding the quantizer). In the proposed DSM structure, the timing limitation on the quantizer and dynamic element matching (DEM) logic in a conventional low-distortion structure can be relaxed from a non-overlapping interval to half of the clock period. A cyclic analog-to-digital converter with a loading-free technique is utilized as a quantizer, which shares an opamp with the active adder. The signal transfer function (STF) is preserved as unity, which means that the integrators process only the quantization noise component. As a result, the opamp used for the integrators has lower requirements, as low-distortion DSMs, on slew rate, output swing, and power consumption. The proposed third-order DSM with a 4-bit cyclic-type quantizer is implemented in a 90-nm CMOS process. Under a sampling rate of 80 MHz and oversampling ratio of 16, simulation results show that an 81.97-dB signal-to-noise and distortion ratio and an 80-dB dynamic range are achieved with 4.17-mW total power consumption. The resulting figure of merit (FOM) is 81.5 fJ/conversion-step.

If a duty ratio, a load resistance and an input voltage in a boost DC-DC converter are changed, the dynamic characteristics are varied greatly, that is, the boost DC-DC converter has non-linear characteristics. In many applications of the boost DC-DC converters, the loads cannot be specified in advance, and they will be changed suddenly from no load to full load. In the boost DC-DC converter, a conventional single controller cannot be adapted to change dynamics and it occurs large output voltage variation. In this paper, an approximate 2-degree-of-freedom (A2DOF) digital controller for suppressing the change of step response characteristics and the variation of an output voltage in load sudden change is proposed. Experimental studies using a micro-processor for the controller demonstrate that this type of digital controller is effective to suppress the variations of the output voltages.

In LDMOS devices for high-voltage applications, there appears a notable fingerprint of current-voltage characteristics known as soft breakdown. Its mechanism is analyzed and modeled on LDMOS devices where a high resistive drift region exists. This analysis has revealed that the softness of breakdown, known as the expansion effect, withholding a run-away of current, is contributed by the flux of holes underneath the gate-overlap region originated by impact-ionization. The mechanism of the expansion effect is modeled and implemented into the compact model HiSIM_HV for circuit simulation. A good agreement between simulated characteristics and 2D-device simulation results is verified.

This paper introduces novel high-speed and low-power boosted level converters for use in dual-supply systems. The proposed level converters adopt a voltage boosting at the gate of pull-down transistors to improve driving speed and reduce contention problem. Comparison results in a 0.13-µm CMOS process indicated that the proposed level converters provided up to 70% delay reduction with up to 57% power-delay product (PDP) reduction as compared to conventional level converters.

A laser irradiation experiment for photocurrent induced failure investigations was described. In order to focus a laser beam on a desired transistor, novel test circuit structures using selectively metal-covered transistors were proposed. Photocurrent induced upset failures were successfully observed in fabricated CMOS SRAM test cells. Results were discussed with SPICE simulations.

A novel type of millimeter/submillimeter wave sampler based on resonant tunneling diodes (RTDs) was proposed, and its operation was confirmed by circuit simulation. It consists of an RTD pulse generator and an RTD detector. Owing to the fuse-like nonlinear I-V curve, highly sensitive sampling can be obtained. We also found that the effects of non-ideality in the I-V curve of the RTD can be corrected by sweeping the DC bias for the RTD detector.