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Advance publication (published online immediately after acceptance)

Volume E83-D No.10  (Publication Date:2000/10/25)

    Regular Section
  • Fault-Tolerant and Self-Stabilizing Protocols Using an Unreliable Failure Detector

    Hiroyoshi MATSUI  Michiko INOUE  Toshimitsu MASUZAWA  Hideo FUJIWARA  

     
    PAPER-Algorithms

      Page(s):
    1831-1840

    We investigate possibility of fault-tolerant and self-stabilizing protocols (ftss protocols) using an unreliable failure detector. Our main contribution is (1) to newly introduce k-accuracy of an unreliable failure detector, (2) to show that k-accuracy of a failure detector is necessary for any ftss k-group consensus protocol, and (3) to present three ftss k-group consensus protocols using a k-accurate and weakly complete failure detector under the read/write daemon on complete networks and on (n-k+1)-connected networks, and under the central daemon on complete networks.

  • Loop Quasi-Invariance Code Motion

    Litong SONG  Yoshihiko FUTAMURA  Robert GLUCK  Zhenjiang HU  

     
    PAPER-Theory and Models of Software

      Page(s):
    1841-1850

    Loop optimization plays an important role in compiler optimization and program transformation. Many sophisticated techniques such as loop-invariance code motion, loop restructuring and loop fusion have been developed. This paper introduces a novel technique called loop quasi-invariance code motion. It is a generalization of standard loop-invariance code motion, but based on loop quasi-invariance analysis. Loop quasi-invariance is similar to standard loop-invariance but allows for a finite number of iterations before computations in a loop become invariant. In this paper we define the notion of loop quasi-invariance, present an algorithm for statically computing the optimal unfolding length in While-programs and give a transformation method. Our method can increase the accuracy of program analyses and improve the efficiency of programs by making loops smaller and faster. Our technique is well-suited as supporting transformation in compilers, partial evaluators, and other program transformers.

  • The Use of High Level Architecture in Car Traffic Simulations

    Atsuo OZAKI  Masakazu FURUICHI  Nobuo NISHI  Etsuji KURODA  

     
    PAPER-Software Systems

      Page(s):
    1851-1859

    Although a number of car-traffic simulators have been developed for various purposes, none of the existing simulators enhance the simulation accuracy using sensor data or allow the system structure to re-configure the system structure depending on the application. Our goal was to develop a highly accurate, highly modular, flexible, and scalable micro-model car-traffic simulation system. The HLA (High Level Architecture) was applied to every system module as a standard interface between each module. This allows an efficient means for evaluating and validating a variety of micro-model simulation schemes. Our ongoing projects consist of running several identical simulations concurrently, with different parameter sets. By sending the results of these simulations to a manager module, which analyzes both the parameter sets and the simulated results, the manager module can evaluate the best-simulated results and determine the next action by comparing these results with the sensor data. In this system, the sensor data or the statistical data on the flow of traffic, obtained by monitoring real roads, is used to improve the simulation accuracy. Future systems are being planned to employ real time sensor data, where the input of the data occurs at almost real time speed. In this paper, we discuss the design of a HLA-based car-traffic simulation system and the construction of a sensor-data fusion algorithm. We also discuss our preliminary evaluation of the results obtained with this system. The results show that the proposed fusion algorithm can adjust the simulation accuracy to the logged sensor data within a difference of 5% (minimum 1.5%) in a specific time period. We also found that simulations with 500 different parameter sets can be executed within 5 minutes using 8 simulator modules.

  • An IDDQ Sensor Driven by Abnormal IDDQ

    Yukiya MIURA  

     
    PAPER-Fault Tolerance

      Page(s):
    1860-1867

    This paper describes a novel IDDQ sensor circuit that is driven by only an abnormal IDDQ. The sensor circuit has relatively high sensitivity and can operate at a low supply voltage. Based on a very simple idea, it requires two additional power supplies. It can operate at either 5-V or 3.3-V VDD with the same design. Simulation results show that it can detect a 16-µA abnormal IDDQ at 3.3-V VDD. This sensor circuit causes a smaller voltage drop and smaller performance penalty in the circuit under test than other ones.

  • Design of C-Testable Modified-Booth Multipliers

    Kwame Osei BOATENG  Hiroshi TAKAHASHI  Yuzo TAKAMATSU  

     
    PAPER-Fault Tolerance

      Page(s):
    1868-1878

    In this paper, we consider the design for testability of a multiplier based on the modified Booth Algorithm. First, we present a basic array implementation of the multiplier. Next, we introduce testability considerations to derive two C-testable designs. The first of the designs is C-testable under the single stuck-at fault model (SAF) with 10 test patterns. And, the second is C-testable under the cell fault model (CFM) with 33 test patterns.

  • Implementation of Quasi Delay-Insensitive Boolean Function Blocks

    Mrt SAAREPERA  Tomohiro YONEDA  

     
    PAPER-Fault Tolerance

      Page(s):
    1879-1889

    The problem of self-timed implementation of Boolean functions is explained. The notions of combinational delay-insensitive code and delay-insensitive function are defined, giving precise conditions under which memoryless self-timed implementation of Boolean functions is feasible. Examples of combinational delay-insensitive code and delay-insensitive function are given. Generic design style, using standard CAD library, for constructing quasi delay-insensitive self-timed function blocks is suggested. Our design style is compared to other self-timed function block design styles.

  • Maximum Likelihood Successive State Splitting Algorithm for Tied-Mixture HMnet

    Alexandre GIRARDI  Harald SINGER  Kiyohiro SHIKANO  Satoshi NAKAMURA  

     
    PAPER-Speech and Hearing

      Page(s):
    1890-1897

    This paper shows how a divisive state clustering algorithm that generates acoustic Hidden Markov models (HMM) can benefit from a tied-mixture representation of the probability density function (pdf) of a state and increase the recognition performance. Popular decision tree based clustering algorithms, like for example the Successive State Splitting algorithm (SSS) make use of a simplification when clustering data. They represent a state using a single Gaussian pdf. We show that this approximation of the true pdf by a single Gaussian is too coarse, for example a single Gaussian cannot represent the differences in the symmetric parts of the pdf's of the new hypothetical states generated when evaluating the state split gain (which will determine the state split). The use of more sophisticated representations would lead to intractable computational problems that we solve by using a tied-mixture pdf representation. Additionally, we constrain the codebook to be immutable during the split. Between state splits, this constraint is relaxed and the codebook is updated. In this paper, we thus propose an extension to the SSS algorithm, the so-called Tied-mixture Successive State Splitting algorithm (TM-SSS). TM-SSS shows up to about 31% error reduction in comparison with Maximum-Likelihood Successive State Split algorithm (ML-SSS) for a word recognition experiment.

  • Image Vector Quantization Using Classified Binary-Tree-Structured Self-Organizing Feature Maps

    Jyh-Shan CHANG  Tzi-Dar CHIUEH  

     
    PAPER-Image Processing, Image Pattern Recognition

      Page(s):
    1898-1907

    With the continuing growth of the World Wide Web (WWW) services over the Internet, the demands for rapid image transmission over a network link of limited bandwidth and economical image storage of a large image database are increasing rapidly. In this paper, a classified binary-tree-structured Self-Organizing Feature Map neural network is proposed to design image vector codebooks for quantizing images. Simulations show that the algorithm not only produces codebooks with lower distortion than the well-known CVQ algorithm but also can minimize the edge degradation. Because the adjacent codewords in the proposed algorithm are updated concurrently, the codewords in the obtained codebooks tend to be ordered according to their mutual similarity which means more compression can be achieved with this algorithm. It should also be noticed that the obtained codebook is particularly well suited for progressive image transmission because it always forms a binary tree in the input space.

  • On Processing Order for Obtaining Implication Relations in Static Learning

    Hideyuki ICHIHARA  Seiji KAJIHARA  Kozo KINOSHITA  

     
    LETTER-Fault Tolerance

      Page(s):
    1908-1911

    Static learning is a procedure to extract implication relations of a logic circuit. In this paper we point out that the number of the extracted implication relations by static learning depends on the order of signal lines processed. Also, we show four procedures for ordering signal lines processed and the effectiveness of the ordering procedures by experiments.