Recently, intelligent heating, next generation microwave ovens that achieve uniform heating and spot heating using solid-state devices, has been actively studied. There are two types of microwave generators using solid-state devices. Since compactness is indispensable to accommodate in a limited space, the miniaturized oscillator type was selected. The authors proposed an imbalanced coupling resonator, a resonator-less feedback circuit, a high power frequency variable resonator, and injection-locked phase control in order to achieve high performance of the oscillator type microwave generator. In addition, we confirmed that the oscillator type can be used as the microwave generator for intelligent heating using a Wilkinson combiner. As a result, it was demonstrated that the oscillator type microwave generator, realized the same high efficiency (67%) as the amplifier type, and found the possibility of variable frequency (2.4 to 2.5GHz) and variable phase, and can be used as the microwave generator for intelligent heating.

Recently, GaN devices are often adopted in microwave power amplifiers to improve the performances. And many new design methods of microwave power amplifier were proposed. As a result, a high-efficiency and super compact microwave signal source has become easily available. It opens up the way for new microwave heating systems. In this paper, the recent progress on design methods of microwave power amplifier and the applications for microwave heating are described. In the first, a device model of GaN transistor is explained. An equivalent thermal model is introduced into the electrical non-linear equivalent device model. In the second, an active load-pull (ALP) measurement system to design a high-efficiency power amplifier is explained. The principle of the conventional closed-loop ALP system is explained. To avoid the risk of oscillation for the closed-loop ALP system, novel ALP systems are proposed. In the third, a microwave heating system is explained. The heating system monitors the reflection wave. Then, the frequency of the signal source and the phase difference between antennas are controlled to minimize the reflection wave. Absorption efficiency of more than 90% was obtained by the control of frequency and phase. In the last part, applications for a medical instrument is described.

A ring-resonator type of electrode (RRTE) has been proposed to detect the circulating tumor cell (CTC) for evaluation of the current cancer progression and malignancy in clinical applications. Main emphasis is placed on the identification sensitivity for the lossy materials that can be found in biomedical fields. At first, the possibility of the CTC detection was numerically considered to calculate the resonant frequency of the RRTE catching the CTC, and it was evident that the RRTE with the cell has the resonant frequency inherent in the cell featured by its complex permittivity. To confirm the numerical consideration, the BaTiO3 particle, whose size was similar to that of the CTC, was inserted in the RRTE instead of the CTC as a preliminary experiment. Next, the resonant frequencies of the RRTE with internal organs of the beef cattle such as liver, lung, and kidney were measured for evaluation of the lossy materials such as the CTC, and degraded Q curves were observed because the Q-factors inherent in the internal organs were usually low due to the poor loss tangents. To overcome such difficulty, the RRTE, the oscillator circuit consisting of the FET being added, was proposed to improve the identification sensitivity. Comparing the identification sensitivity of the conventional RRTE, it has been improved because the oscillation frequency spectrum inherent in an internal organ could be easily observed thanks to the oscillation condition with negative resistance. Thus, the validity of the proposed technique has been confirmed.

This paper presents two ultra-low voltage and high performance VCO ICs with two novel transformer-based harmonic tuned tanks. The first proposed harmonic tuned tank effectively shapes the pseudo-square drain-node voltage waveform for close-in phase noise reduction. To compensate the voltage drop caused by the transformer, an improved second tank is proposed. It not only has tuned harmonic impedance but also provides a voltage gain to enlarge the output voltage swing over supply voltage limitation. The VCO with second tank exhibits over 3 dB better phase noise performance in 1/f² region among all tuning range. The two VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With only 0.3 V supply voltage, the proposed two VCO ICs exhibit best phase noise of -123.3 and -127.2 dBc/Hz at 10 MHz offset and related FoMs of -191.7 and -192.2 dBc/Hz, respectively. The frequency tuning ranges of them are from 14.05 to 15.14 GHz and from 14.23 to 15.68 GHz, respectively.

Smaller antenna structures for long-range radar transmitters and receivers operating in the 77-GHz band for automotive application have been achieved by using antennas with a horn, lens, and microstrip antenna. The transmitter (Tx) antenna height was reduced while keeping the antenna gain high and the antenna substrate small by developing an antenna structure composed of two differential horn and lens antennas in which the diameter and focus distance of the lenses were half those in the previous design. The microstrip antennas are directly connected to the differential outputs of a monolithic microwave integrated circuit. A Tx antenna fabricated using commercially available materials was 14mm high and had an output-aperture of 18×44mm. It achieved an antenna gain of 23.5dBi. The antenna substrate must be at least 96mm². The antenna had a flat beam with half-power elevation and azimuth beamwidths of 4.5^° and 21^°, respectively. A receiver (Rx) antenna array composed of four sets of horn and lens antennas with an output-aperture of 9×22mm and a two-by-two array configuration was fabricated for application in a newly proposed small front-end module with azimuth direction of arrival (DOA) estimation. The Rx antenna array had an antenna coupling of less than -31dB in the 77-GHz band, which is small enough for DOA estimation by frequency-modulated continuous wave radar receivers even though the four antennas are arranged without any separation between their output-apertures.

This paper presents analysis results of the intermodulation distortion (IMD) components compensation conditions for dual-band feed-forward power amplifier (FFPA) when inputting dual-band signals simultaneously. The signal cancellation loop and distortion cancellation loop of the dual-band FFPA have frequency selective adjustment paths which consist of filter and vector regulator. The filter selects the desired frequency component and suppresses the undesired frequency component in the desired frequency selective adjustment path. The vector regulators repeatedly adjust the amplitude and phase values of the composite components for the desired and suppressed undesired frequency components. In this configuration, the cancellation levels of the signal cancellation loop and distortion cancellation loop are depending on the amplitude and phase errors of the vector regulator. The analysis results show that the amplitude and phase errors of the desired frequency component almost become independent that of the undesired frequency component in a weak non-linearity condition, when the isolation between the desired band and the undesired band given by the filter is more than 40 dB. The amplitude errors of the desired frequency component are dependent on that of the undesired frequency component in a strong non-linear conditions when the isolation level sets as above. A 1-W-class signal cancellation loop and 20-W-class FFPA are fabricated for 1.7-GHz and 2.1-GHz bands simultaneous operation. The experimental results show that the analysis results are suitable in the experimental conditions. From these investigations, the analysis results can provide a commercially available dual-band FFPA. To our best knowledge, this is first analysis results for the dual-band FFPA.

This paper discusses and elaborates an analytical model of a multi-stage switched-capacitor (SC) voltage boost converter (VBC) for low-voltage and low-power energy harvesting systems, because the output impedance of the VBC, which is derived from the analytical model, plays an important role in the VBC's performance. In our proposed method, we focus on currents flowing into input and output terminals of each stage and model the VBCs using switching frequency f, charge transfer capacitance C_F, load capacitance C_L, and process dependent parasitic capacitance's parameter k. A comparison between simulated and calculated results showed that our model can estimate the output impedance of the VBC accurately. Our model is useful for comparing the relative merits of different types of multi-stage SC VBCs. Moreover, we demonstrate the performance of a prototype SC VBC and energy harvesting system using the SC VBC to show the effectiveness and feasibility of our proposed design guideline.

Chopping technique up-modulates amplifier's offset and low-frequency noise up to its switching frequency, and therefore can achieve low offset and low temperature drift. On the other hand, it generates unwanted AC and DC errors due to its switching artifacts such as up-modulated ripple and glitches. This paper summarizes various circuit techniques of reducing such switching artifacts, and then discusses the advantages and disadvantages of each technique. The comparison shows that newer designs with advanced circuit techniques can achieve lower DC and AC errors with higher chopping frequency.

This paper proposes an ultra-low quiescent current low-dropout regulator (LDO) with a flipped voltage follower (FVF)-based load transient enhanced circuit for wireless sensor network (WSN). Some characteristics of an FVF are low output impedance, low voltage operation, and simple circuit configuration [1]. In this paper, we focus on the characteristics of low output impedance and low quiescent current. A load transient enhanced circuit based on an FVF circuit configuration for an LDO was designed in this study. The proposed LDO, including the new circuit, was fabricated in a 0.6 µm CMOS process. The designed LDO achieved an undershoot of 75 mV under experimental conditions of a large load transient of 100 µA to 10 mA and a current slew rate (SR) of 1 µs. The quiescent current consumed by the LDO at no load operation was 204 nA.

This paper proposes and demonstrates a 65nm CMOS process cascode single-inductor-dual-output (SIDO) boost converter whose outputs are Li-ion battery and 1V low voltage supply for RF wireless power transfer (WPT) receiver. The 1V power supply is used for internal control circuits to reduce power consumption. In order to withstand 4.2V Li-ion battery output, cascode 2.5V I/O PFETs are used at the power stage. On the other hand, to generate 1V while maintaining 4.2V tolerance at 1V output, cascode 2.5V I/O NFETs output stage is proposed. Measurement results show conversion efficiency of 87% at P_IN=7mW, I_LOAD=1.6mA and V_BAT=4.0V, and 89% at P_IN=7.9mW, I_LOAD=2.1mA and V_BAT=3.4V.

Hum noise such as power line interference is one of the critical problems in the biomedical signal acquisition. Various techniques have been proposed to suppress power line interference. However, some of the techniques require more components and power consumption. The notch depth in the conventional N-path notch filter circuits needs a higher number of paths and switches off-resistance. It makes the conventional N-path notch filter less of efficiency to suppress hum noise. This work proposed the new N-path notch filter to hum noise suppression in biomedical signal acquisition. The new N-path notch filter achieved notch depth above 40dB with sampling frequency 50Hz and 60Hz. Although the proposed circuits use less number of path and switches off-resistance. The proposed circuit has been verified using artificial ECG signal contaminated by hum noise at frequency 50Hz and 60Hz. The output of N-path notch filter achieved a noise-free signal even if the sampling frequency changes.

This paper presents a design of CMOS transimpedance amplifier (TIA) and peaking inductor for high speed, low power and small area. To realize high density integration of optical I/O, area reduction is an important figure as well as bandwidth, power and so on. To determine design parameters of multi-stage inverter-type TIA (INV-TIA) with peaking inductors, we derive a simplified model of the bandwidth and the energy per bit. Multi-layered on-chip inductors are designed for area-effective inductive peaking. A 5-stage INV-TIA with 3 peaking inductors is fabricated in a 65-nm CMOS. By using multi-layered inductors, 0.02 mm² area is achieved. Measurement results show 45 Gb/s operation with 49 dBΩ transimpedance gain and 4.4 mW power consumption. The TIA achieves 98 fJ/bit energy efficiency.

With increasing technology scaling and the use of lower voltages, more research interest is being shown in variability-tolerant analog front end design. In this paper, we describe an adaptive amplitude control transmitter that is operated using differential signaling to reduce the temperature variability effect. It enables low power, low voltage operation by synergy between adaptive amplitude control and V_th temperature variation control. It is suitable for high-speed interface applications, particularly cable interfaces. By installing an aggressor circuit to estimate transmitter jitter and changing its frequency and activation rate, we were able to analyze the effects of the interface block on the input buffer and thence on the entire system. We also report a detailed estimation of the receiver clock-data recovery (CDR) operation for transmitter jitter estimation. These investigations provide suggestions for widening the eye opening of the transmitter.

This paper presents a miniaturized transformer-based ultra-low-power (ULP) LC-VCO with embedded supply pushing reduction techniques for IoT applications in 65-nm CMOS process. To reduce the on-chip area, a compact transformer patterned ground shield (PGS) is implemented. The transistors with switchable capacitor banks and associated components are placed underneath the transformer, which further shrinking the on-chip area. To lower the power consumption of VCO, a gm-stacked LC-VCO using the transformer embedded with PGS is proposed. The transformer is designed to provide large inductance to obtain a robust start-up within limited power consumption. Avoiding implementing an off/on-chip Low-dropout regulator (LDO) which requires additional voltage headroom, a low-power supply pushing reduction feedback loop is integrated to mitigate the current variation and thus the oscillation amplitude and frequency can be stabilized. The proposed ULP TF-based LC-VCO achieves phase noise of -114.8dBc/Hz at 1MHz frequency offset and 16kHz flicker corner with a 103µW power consumption at 2.6GHz oscillation frequency, which corresponds to a -193dBc/Hz VCO figure-of-merit (FoM) and only occupies 0.12mm² on-chip area. The supply pushing is reduced to 2MHz/V resulting in a -50dBc spur, while 5MHz sinusoidal ripples with 50mV_PP are added on the DC supply.

Many studies of deep neural networks have reported inference accelerators for improved energy efficiency. We propose methods for further improving energy efficiency while maintaining recognition accuracy, which were developed by the co-design of a filter-by-filter quantization scheme with variable bit precision and a hardware architecture that fully supports it. Filter-wise quantization reduces the average bit precision of weights, so execution times and energy consumption for inference are reduced in proportion to the total number of computations multiplied by the average bit precision of weights. The hardware utilization is also improved by a bit-parallel architecture suitable for granularly quantized bit precision of weights. We implement the proposed architecture on an FPGA and demonstrate that the execution cycles are reduced to 1/5.3 for ResNet-50 on ImageNet in comparison with a conventional method, while maintaining recognition accuracy.

This paper presents a large-angle imaging algorithm based on a dynamic scattering model for inverse synthetic aperture radar (ISAR). In this way, more information can be presented in an ISAR image than an ordinary RD image. The proposed model describes the scattering characteristics of ISAR target varying with different observation angles. Based on this model, feature points in each sub-image of the ISAR targets are extracted and matched using the scale-invariant feature transform (SIFT) and random sample consensus (RANSAC) algorithms. Using these feature points, high-precision rotation angles are obtained via joint estimation, which makes it possible to achieve a large angle imaging using the back-projection algorithm. Simulation results verifies the validity of the proposed method.

In this study, the transient characteristics on the super-steep subthreshold slope (SS) of a PN-body tied (PNBT) silicon-on-insulator field-effect transistor (SOI-FET) were investigated using technology computer-aided design and pulse measurements. Carrier charging effects were observed on the super-steep SS PNBT SOI-FET. It was found that the turn-on delay time decreased to nearly zero when the gate overdrive-voltage was set to 0.1-0.15 V. Additionally, optimizing the gate width improved the turn-on delay. This has positive implications for the low speed problems of this device. However, long-term leakage current flows on turn-off. The carrier lifetime affects the leakage current, and the device parameters must be optimized to realize both a high on/off ratio and high-speed operation.

For automotive millimeter radar, a method using a multi-input multi-output (MIMO) array antenna is essential for high angle resolution with module miniaturization. MIMO enables us to extend an antenna array with virtual antennas, and a large antenna array aperture enables high resolution angle estimation. Time division multiplex (TDM) MIMO, which is a method to generate virtual array antennas, makes it easy to design radar system integrated circuits. However, this method leads to two issues in signal processing; the phase error reduces the accuracy of angle estimation of a moving target, and the maximum detectable velocity decreases in inverse proportion to the number of Tx antennas. We analytically derived this phase error and proposed a method to correct the error. Because the phase error of TDM-MIMO is proportional to the target velocity, accurate estimation of the target velocity is an important issue for phase error correction. However, the decrease of the maximum detectable velocity in TDM-MIMO reduces the accuracy of both velocity estimation and angle estimation. To solve these issues, we propose new signal processing for range-velocity estimation for TDM-MIMO radar. By using the feedback result of the estimated direction of arrival (DoA), we can avoid decreasing the maximum detectable velocity. We explain our method with our simulation results.

Recently, we demonstrated a rapid-single-flux-quantum NOT gate comprising a toggle storage loop. In this paper, we present our design and operation of a NOR gate that is a straightforward extension of the NOT gate by attaching a confluence buffer. Parameter margins wider than ±28% were confirmed in simulation. Functional tests using Nb integrated circuits demonstrated correct NOR operation with a bias margin of ±21%.