Hot carrier reliability due to residual damage in the gate oxide created by synchrotron X-ray irradiation is investigated for subquarter-micrometer NMOSFETs under a wide irradiation-dose range (103,000 mJ/cm²). Although irradiation-induced interface-traps and positive charges are completely eliminated after 400 post-metalization-annealing, neutral electron traps partially remain. The effects of the residual trapa on hot-carrier degradation can be negligible when gate oxides thinner than about 5 nm are used, and it is found that there is no effect of irradiation damage on interface-trap generation due to injected hot-carriers. It is concluded that the influence of synchrotron radiation X-ray lithography on hot-carrier-induced degradation in subquarter-micrometer NMOSFETs can be negligible.

Two kinds of nitrided ultrathin (510 nm) SiO₂ films were formed on the silicon (100) face using rapid thermal NH₃-nitridation (RTN) and rapid thermal N₂O-oxynitridation (RTON) technologies. The MOS capacitors with RTN SiO₂ film showed that by Fowler-Nordheim (F-N) electron injection, both electron trap density and low-field leakage increase by the NH₃-nitridation. In addition, the charge-to-breakdown (Q_BD) value decreases owing to NH₃-nitridation. By contrast, RTON SiO₂ films exhibited extremely low electron trap density, almost no increase of the leakage current, and large Q_BD value above 200C/cm². The oxide film composition was evaluated by secondary ion mass spectroscopy (SIMS). The chemical bonding states were also examined by Fourier transform-infrared reflection attenuated total reflectance (FT-IR ATR) and X-ray photoelectron spectroscopy (XPS) measurements. These results indicate that although a large number of nitrogen (N) atoms are incorporated by the RTN and RTON, only the RTN process generates the hydrogen-related species such as NH and SiH bounds in the film, whereas the RTON film indicates only SiN bonds in bulk SiO₂. From the dielectric and physical properties of the oxide films, it is considered that the oxide wearout by high-field stress is the result of the electron trapping process, in which anomalous leakage due to trap-assisted tunneling near the injected interface rapidly increases, leading to irreversible oxide failure.

A new technique for evaluating gate oxide reliability using photon emission method has been developed. This method enables the measurements of the initial breakdown characteristics, reliability testing and failure analysis consistently. From the experimental results, followings are clarified for the first time using this technique. Failure modes in the initial characteristics have close correlation to TDDB characteristics and both characteristics correspond to the location of breakdown spot. The results suggest measures to improve the reliability of gate oxide and the existance of new failure mechanism.

A CMOS design to achieve high drivability is examined for lower power supply voltage in 0.5 µm ULSI. The design consists of two points. (1) A very narrow (50 nm) sidewall is used to achieve high drivability and also to obtain hot-carrier-reliability. (2) A retrograded channel profile with NMOS and PMOS is designed to achieve high drivability and also to reduce short channel effect. It is shown that the propagation delay times (tpd) of a unloaded Inverter and a loaded 2-way NAND gate are improved 30% with the newly designed CMOS, compared with the conventionally designed CMOS. It is also proved that the tpd keeps the scaling trend of the previous-5 V-era even in 3.3 V-era by adapting the newly designed CMOS. Moreover, 7.1 ns multiplication time of 1616-bit multiplier is obtained under 0.5 µm design rule.

A novel CMOS structure has been developed using Ti-salicide PSD transistor formed by a new self-aligned method. Both N-channel and P-channel PSD transistors exhibit excellent short-channel behaviors down to the sub-half-micrometer region with shallow S/D junctions formed by dopant diffusion from polysilicons. New salicide process has been developed for the PSD structure and can effectively reduce the sheet resistances of the S/D polysilicon and the polysilicon gate to as low as 45Ω/. As a result, the low resistive local interconnects can be successfully implemented by the Ti-salicide S/D polysilicon merged with contacts by self-alignment. More-over it is found that shallow Ti-salicide S/D junctions with the PSD structure can achieve approximately 12 orders of magnitude lower area leakage current than that of the conventional implanted S/D junctions by eliminating implanted damage and preventing penetration of silicide into junctions with the elevated structure of S/D polysilicon layer. Furthermore CMOS ring oscillators having PSD transistors with an effective channel length of 0.4 µm were fabricated using the salicided S/D polysilicon as a local interconnect between the N⁺ and the P⁺ regions, and successfully operated with a propagation delay time of 50 ps/stage at a supply voltage of 5 V.

Self-aligned aluminum-gate MOSFET's have been successfully fabricated by employing ultraclean ion implantation technology. The use of ultra high vacuum ion implanter and the suppression of high-energy ion-beam-induced metal sputter contamination have enabled us to form ultra-shallow low-leakage pn junctions by furnace annealing at a temperature as low as 450. The fabricated aluminum-gate MOSFET's have exhibited good electrical characteristics, thus demonstrating a large potential for application to realizing ultra-high-speed integrated circuits.

A new capacitor over bit-line (COB) stacked capacitor memory cell was developed using a local interconnect poly-silicon layer to arrange a capacitor contact between bit-lines. This memory cell enables usable capacitor area to increase and capacitor contact hole depth to decrease. The hemispherical grain (HSG) silicon, whose effective surface area is twice that of ordinary poly-silicon, was utilized for the storage node to increase the storage capacitance without increasing the storage node height. The feasibility of achieving a 1.8 µm² memory cell with 30 fF storage capacitance using a 7 nm-SiO₂-equivalent dielectric film and a 0.5 µm-high HSG storage node has been verified for 64 MbDRAMs by a test memory device using a 0.4 µm CMOS process.

The concentration of the electric field at the edge of the electrode has been simulated in several types of flat DRAM cell capacitors with high permittivity dielectrics. The results indicated that the permittivity of the material surrounding the edge of the electrode as well as the geometrical structure affected the concentration of the electric field. The electric field strength was minimized and most evenly distributed by utilizing the structure in which the sidewall of the capacitor dielectric was terminated at the edge of the electrode by a low-dielectric constant insulator. High-precision fabrication of the capacitor's profile is required for the minimization and uniformity of the electric field.

We designed and fabricated a prototype 0.4-µm-gate CMOS/SIMOX PLL LSI in order to verify the potential usefulness of ultrathin-film SIMOX technology for creating an extremely low-power LSI containing high-speed circuits operating at frequencies of at least 1 GHz and at low supply voltages. This PLL LSI contains both high-frequency components such a prescaler and low-frequency components such as a shift register, phase frequency comparator, and fixed divider. One application of the LSI could be for synthesizing communication band frequencies in the front-end of a battery-operated wireless handy terminal for personal communications. At a supply voltage of 2 V, this LSI operates at up to 2 GHz while dissipating only 8.4 mW. Even at only 1.2 V, 1 GHz-operation can be obtained with a power consumption of merely 1.4 mW. To explain this low-power feature, we extensively measured the electrical characteristics of individual CMOS/SIMOX basic circuits as well as transistors. Test results showed that the high performance of the LSI is mainly due to the advanced nature of the CMOS/SIMOX devices with low parasitic capacitances around source/drain regions and to the new circuit design techniques used in the dual-modulus prescalar.

We propose a high-speed SOI bipolar transistor fabricated using bonding and thinning techniques. It is important to replace SOI area except for devices with thick SiO₂ to reduce parasitic capacitance. A thin SOI film with a thin buried layer helps meet this requirement. We formed a 1-µm-thick SOI film with a 0.7-µm-thick buried layer by ion implantation before wafer bonding pulse-field-assisted bonding and selective polishing. Devices were completely isolated by thick SiO₂ using a thin SOI film and the LOCOS process. We fabricated epitaxial base transistors (EBTs) on bonded SOI. Our transistors had a cutoff frequency of 32 GHz.

Selective epitaxial growth technology has been extended to the base formation of a transistor on the basis of the SATURN (Self-Alignment Technology Utilizing Reserved Nitride) process, a high-speed bipolar LSI processing technology. The formation of a self-aligned base contact, coupled with SIC (Selective Ion-implanted Collector) fabricated by lowenergy ion implantation, has not only narrowed the transistor active regions but has drastically reduced the base width. A final base width of 800 and a maximum cut-off frequency of 31 GHz were achieved.

This paper describes the potential of KrF excimer laser lithography for the development and production of 64 M and 256 Mbit DRAMs on the basis of our recent developed results. Quarter micron KrF excimer laser lithography has been developed. A new chemically amplified positive resist realizes high stability and process compatibility for 0.25 micron line and space patterns and 0.35 micron contact hole patterns. This developed resist is characterized as the increase of dissolution characteristics in exposed areas, and hence means the high resolution is obtained. A multiple interference effect was greatly reduced by using our over coat film or anti-reflective coating. This over coat film has no intermixing to the resist and it is simultaneously removed when the resist is developed. This anti-reflective coating has low etch selectivity to the resist, and hence the over coat film is etched away when etching the substrate. The two major results indicate that the KrF excimer laser lithography is promising for the development of 256 MDRAMs.

A glass precursor resist (GPR) is designed on the basis of an idea of conversion of organosilicon polymer to an inorganic substance by lithographic procedure. Developed chemical amplification resist system is composed of poly (di-t-butoxysiloxane) and a photoacid generator. It has a high sensitivity of 1.6 µC/cm², a resolution of 0.2 µm and an extremely high O₂-RIE durability compared with bottom resist. Exposed film changed into silicate glass, and it was confirmed by IR spectra.

The minimum transferable linewidth by X-ray is derived using waveguide analysis. The minimum width is determined by the refractive index of the absorber and does not depend on the X-ray wavelength. Therefore there is an optimum mask aperture size which provides the minimum linewidth. By using Au as the absorber, 8 nm linewidth is attainable.

Practical linewidth measurement accuracy better than 0.02 µm 3 sigma that meets the production requirement for devices with sub-half micron features, was achieved in a field emission scanning electron-beam metrology system (Hitachi S-7000). In order to establish high accuracy linewidth measurement, it was found in the study that reduction of electron-beam diameter and precise control of operating conditions are significantly effective. For the purpose of reducing electron-beam diameter, a novel electron optical system was adopted to minimize the chromatic aberration which defines electron-beam profile. As a result the electron beam diameter was reduced from 20 nm to 16 nm. In order to reduce measurement uncertainties associated with actual operating conditions, a field emission electron gun geometry and an objective lens current monitor were investigated. Then the measurement uncertainties due to operating conditions was reduced from 0.016 µm to 0.004 µm.

The effects of low temperature etching for sub-half micron multi-layer resist are investigated. The low temperature etching with pure O₂ gas provides higher anisotropic profiles than with an additional gas such as Cl₂, N₂. This is caused by the difference in the formative process of the side wall protection. With pure O₂ gas at 80, highly anisotropic profiles for 0.35 µm patterns can be performed while the maximum tolerable width loss is below 0.03 µm.

Phosphorus-doped amorphous or polycrystalline silicon can yield a conformal, low resistance, thermallystable plug for the high-aspect-ratio, sub-half-micron contactholes found in current development prototypes of future 64 and 256 Mega-bit DRAMs. When directly contacted to a silicide layer, however, such as WSi_x found in polycide gate or bit line metallization/contact structures, the outdiffusion of phosphorus from the doped-silicon layer into the silicide can occur, resulting in an increase in resistance. The characteristics of both the doped-silicon and WSi_x layers influence the outdiffusion. The grain size of the doped silicon appears to control diffusion at the WSi_x/doped-silicon interface while the transition of WSi_x from an as-deposited amorphous to a post-annealed polycrystalline state appears to help cause uniform phosphorus diffusion throughout the silicide film. The results of phosphorus pre-doping of the silicide to reduce the effects of outdiffusion are dependent upon the relative material volumes and interfacial areas of the layers. Due to the effectiveness of the TiN barrier layer/Ti contact layer structure used in Al-based contacts, Ti and TiN were evaluated on their ability to prevent phosphorus outdiffusion. Ti reacts easily with doped silicon and to some extent with WSi_x, thereby allowing phosphorus to outdiffuse through the TiSi_x into the overlying WSi_x. TiN, however, is very effective in preventing phosphorus outdiffusion and preserving polycide interface smoothness. A WSi_x/TiN/Ti metallization layer on an in situ-doped (ISD) silicon layer with ISD silicon-plugged contactholes yields contact resistances comparable to P⁺-implanted or non-implanted WSi_x layers on similar ISD layers/plugs for contact sizes greater than approximately 0.5 µm but for contacts of 0.4 µm or below the trend in contact resistance is lowest for the polycide with TiN barrier/Ti contact interlayers. A 20 nm-thick TiN film retains its barrier characteristics even after a 4-hour 850 anneal and is applicable to the silicide-on-doped-silicon structures of future DRAM and other ULSI devices.

The performance of copper interconnects formed by the low-kinetic-energy ion bombardment process has been investigated. The copper films formed on SiO₂ by this technology under a sufficient amount of ion energy deposition exhibit perfect orientation conversion from Cu (111) to Cu (100) upon post-metallization thermal annealing. We have discovered such crystal orientation conversion is always accompanied by a giant-grain growth as large as 100 µm. The copper film resistivity decreases due to the decrease in the grain boundary scattering, when the giant-grain growth occurs in the film. The resistivity of giant-grain copper film at a room temperature is 1.76 µΩcm which is almost equal to the bulk resistivity of copper. Furthermore, a new-accelerated electromigration life-test method has been developed to evaluate copper interconnects having large electromigration resistance within a very short period of test time. The essence of the new method is the acceleration by a large-current-stress of more than 10⁷ A/cm² and to utilize the self heating of test interconnect for giving temperature stress. In order to avoid uncontrollable thermal runaway and resultant interconnect melting, we adopted a very efficient cooling system that immediately removes Joule heat and keeps the interconnect temperature constant. As a result, copper interconnects formed by the low-kinetic-energy ion bombardment process exhibit three orders of magnitude longer lifetime at 300 K than Al alloy interconnects.

Copper contamination behavior is studied, depending on the pH level, conductivity type P or N of a silicon substrate, and contamination method of copper. If the pH level of a copper containing solution is adjusted by using ammonia, copper atoms and ammonia molecules produce copper ion complexes. Accordingly, the amount of copper adsorption on the substrate surface is decreased. When N-type silicon substrates are contaminated by means of copper containing solutions, copper atoms on the surfaces diffuse into bulk crystal even at room temperature. But for P-type silicon substrates, copper atoms are transferred into bulk crystal only after high temperature annealing. In the case of silicon substrates contaminated by contact with metallic copper, no copper atom diffusion into bulk crystal was observed. The above mentioned copper contamination behavior can be explained by the charge transfer interaction of copper atoms with silicon substrates.

A new redundancy technique especially suitable for ultra-high-speed static RAMs (SRAMs) has been developed. This technique is based on a decoding-method that uses two kinds of fuses without introducing any additional delay time. One fuse is initially ON and can be turned OFF afterwards, if necessary, by a cutting process using a focused ion beam (FIB). The other is initially OFF and can be turned ON afterwards by a connecting process using laser chemical vapor deposition (L-CVD). This technique is applied to a 64 kbit SRAM having a 1.5-ns access time. The experimental results obtained through an SRAM chip repaired using this redundancy technique show that this technique does not introduce any increase in the access time and does not reduce the operational margin of the SRAM.

In this paper, boundary integral equations are derived from the Green's identity of the second kind in circular cylindrical coordinates, and are applied to determine the resonant frequencies of shielded circular ring and disk resonators. The integral equations are numerically solved by discretizating the integration path representing the air-dielectric interface and the surface of thick strip conductor. Because of the choice of the eigen-functions as weighted functions instead of Green's functions, the overall integral path length is shortened and computational time is reduced. Computational results on thick circular disk and ring resonators are compared with other available numerical results and experimental data.

It is shown from a computer analysis that there exists a resonant mode of a surface wave which propagates along Goubau line, and that the attenuation of such a mode is very low. The approximate formula for obtaining the resonant frequency is also given.