This paper designs recursive least-squares fixed-point smoother and filter, which use the observed value, the probability that the signal exists, and the covariance information relevant to the signal and observation noises, on the estimation problem associated with the uncertain observations in linear continuous-time systems.

We have fabricated a new analog memory for integrated artificial neural networks. Several attempts have been made to develop a linear characteristics of floating-gate analog memorys with feedback circuits. The learning chip has to have a large number of learning control circuit. In this paper, we propose a new analog memory SDAM with three cascaded TFTs. The new analog memory has a simple design, a small area occupancy, a fast switching speed and an accurate linearity. To improve accurate linearity, we propose a new chargetransfer process. The device has a tunnel junction (poly-Si/poly-Si oxide/poly-Si sandwich structure), a thin-film transistor, two capacitors, and a floating-gate MOSFET. The diffusion of the charges injected through the tunnel junction are controlled by a source follower operation of a thin film transistor (TFT). The proposed operation is possible that the amounts of transferred charges are constant independent of the charges in storage capacitor.

In this paper, a simple method to investigate the dynamics of continuous-time neural networks based on the force (kinetic vector) derived from the equation of motion for neural networks instead of the energy function of the system has been described. The number of equilibrium points and limit cycles of one-dimensional neural networks with the asymmetric cyclic connection matrix has been investigated experimently by this method. Some types of equilibrium points and limit cycles have been theoretically analyzed. The relations between the properties of limit cycles and the number of connections also have been discussed.

Discrete-time chaotic circuits realizing a tent map and a Bernoulli map are synthesized using switched-current (SI) techniques. For these proposed circuits, simulations are performed concerning the return maps and bifurcation trees. The theoretical analysis is carried out to predict the bifurcation tree under the existence of the nonidealities in the return map. This analysis has been done by assuming the return maps to be piecewise linear. The proposed circuits are built with commerciallyavailable IC's. And their return maps and bifurcation trees are measured in the experiment. The design formulas are obtained for the bifurcation trees and they are confirmed by the simulation results. The proposed circuits are integrable by a standard BiCMOS technology.

In this paper,novel techniques for designing Finite Impulse Response (FIR) digital integrators have been given. The design is based on analytical approach for computing the weights required in the structures. Exact mathematical formulas for computing these weights have been derived.

In this paper, a super-resolution method based on the Discrete Cosine Transform (DCT) is proposed for a signal with some frequency damage. If the damage process can be modeled as linear convolutoin with a type 1 linear phase FIR filter, it is shown that some DCT coefficients of the damaged signal are the same as those of the original signal except for the DCT coefficients corresponding to the frequency damage. From this investigation, the proposed method is provided for the DCTs with four types as expanding the super-resolution method based on the Discrete Fourier Transform (DFT). In addition,two magnification approaches based on the proposed method are described to improve the conventional approach.

We propose a speech recognition method using fusion of auditory and visual information for accurate speech recognition. Since we use both auditory information and visual information, we can perform speech recognition more accurately in comparison with the case of either auditory information or visual information. After processing each information by HMM, they are fused by linear combination with weight coefficient. We performed experiments and confirmed the validity of the proposed method.

A blind equalization algorithm which makes use of the Stop" region of the Stop-and-Go algorithm is proposed. By adaptively updating the tap weights at the Stop region as well, it is intended to improve the convergence property of the Stop-and-Go algorthm. The performance of the proposed algorithm is compared with the conventional Stop-and-Go algorithm using various communication channels. Simulation results indicate the improvement of the convergence speed while maintaining or possibly lowering the residual error.

This paper presents the computer simulation results on frequency reuse efficiency and soft handoff statistics in the CDMA forward link according to path loss and cell loading. The soft handoff threshold effect on the handoff statistics is also evaluated. The frequency reuse efficiency is not a fixed value but varying as function of distance from the home cell, path loss slopes, and cell loading. The total soft handoff pecentile ranges from 0.0 to 64.9 according to cell loading, even if path loss slope is constant.

An analysis of an imperfectly power controlled DS/CDMA slotted cellular system over the frequency selective Rician fading channel with an error correction coding is performed. The user capacity and packet throughput of reverse link are estimated to show the sensitivity to the power control error in a DS/CDMA system with Rician fading channel. The power control error are modeled with Gaussian random variables, which is a reasonable choice for its proved validity. The relative capacity decrease from the power control error in Rician channel are presented and compared with the results from flat fading channel. Performance results for the model considering multicell interference, pathloss exponent and power ratio of scattered component to direct component are presented.

In this paper, we design an optimized compensation transaction (OCT) that implies an important property of location information. The validity of the proposed compensation transaction is illustrated by describing the HLR database systems on the mobile telecommunications system. We found out that both the length and the occurrence percentage of compensation transactions affect reversely the success ratio of other transactions. However, OCT rarely affects the other transactions, because the compensating procedures are performed rapidly. This paper argues that the optimized compensation transaction is very adequate in the mobile telecommunication system where update transactions are issued more frequently than read-only transactions.

A data-flow program net is a graph representation of data-flow programs consisting of three types of nodes, AND-node, OR-node and SWITCH-node, which represent arithmetic/logical, data merge and context switch operations respectively. Token self-cleanness is an important property of a data-flow program and is such that if date-flow programs satisfy the property then a date-flow computer can efficiently withdraw copies from given programs during executions. In this paper, we classify program nets into SWITCH-less, OR-less and general nets, and analyse structures of data-flow program nets to propose verification methods of token self-cleanness by investigating token numbers appearing on the edges. As a result, a necessary and sufficient condition is proposed for SWITCH-less data-flow program nets and sufficient conditions are given for OR-less and general data-flow program nets.

Signal Transition Graphs (STG'S) [1] are Petrinets [2], which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets (OCN) and its prefix, called unfollding, has been proposed [3], [4]. OCN's can represent both causality and concurrency between two nodes by net stryctyre. In this paper, we propose an efficient algorithm to derive a logic function by generating sub-state space of a given STG using the structural properties of OCN. The proposed algorithm can be seem as a parallel algorithm for deriving a logic function.

When we use a telephone-handset, the frequency response of the telephone-earphone becomes degraded because of the leak through the slit between the ear and the earphone. Consequently, it is very important to establish the design method of the telephone-handset which reduces the effect of leak. No one has tried to design the telephone-handset to reduce the effect. We are the only ones to have proposed an automatic design method by nonlinear optimization techniques. However, this method gives only one set of the acoustic parameters aiming at a certain specific target frequency response, and therefore lacks flexibility in the actual design problem. On the other hand, the design method proposed in this paper, which uses Monte-Carlo method, gives an infinite number of sets of acoustic parameters that realize infinite frequency responses within the target allowable region. As these infinite number of sets become directly the design ranges of acoustic parameters, the proposed method has the flexibility that any set of the acoustic parameters belonging to the design ranges guarantees the corresponding response to be within the target allowable region, and at the same time reduces the effect of leak. This flexibility is advantageous to the actual design problem.

A CMOS fully balanced current-mode filter is presented. A fully balanced current-mode integrator which is the basic building block is implemented by adding a very simple common-mode-rejection mechanism to fully differential one. The fully balanced operation can eliminate even order distortion, which is one of the drawbacks in previous continuous current-mode filter. Moreover, the additional circuit can work as not only common-mode-rejection mechanism but also Q-tuning circuit which compensates lossy elements due to finite output impedance of MOS FET. A prototype fifth-order low-pass lad-der filter designed in a standard digital 0.8µm CMOS process achieved a cut-off frequency (fC) of 100MHz; fC was tunable from 75MHz to 120MHz by varying a reference bias current from 50µA to 150µA. Using a single 3V power supply with a nominal reference current of 100µA, power dissipation per one pole is 30mW. The active filter area was 0.011mm²/pole and total harmonic distortion (THD) was 0.73 [%] at 80MHz, 80µA amplitude signal. Furthermore, by adjusting two bias currents, on chip automatic both frequency and Q controls are easily implemented by typical tuning systems, for example master-slave tuning systems [1].

We present a systematic theory for the optimum sub-band interpolation using a given analysis or synthesis filter bank with the prescribed coefficient bit length. Recently, similar treatment is presented by Kida and quantization for decimated sample values is contained partly in this discussion [13]. However, in his previous treatment, measures of error are defined abstractly and no discussion for concrete functional forms of measures of error is provided. Further, in the previous discussion, quantization is neglected in the proof of the reciprocal theorem. In this paper, linear quantization for decimated sample values is included also and, under some conditions, we will present concrete functional forms of worst case measures of error or a pair of upper bound and lower limit of those measures of error in the variable domain. These measures of error are defined in Rⁿ, although the measure of error in the literature [13] is more general but must be defined in each limited block separately. Based on a concrete expression of measure of error, we will present similar reciprocal theorem for a filter bank nevertheless the quantization for the decimated sample values is contained in the discussion. Examples are given for QMF banks and cosine-modulated FIR filter banks. It will be shown that favorable linear phase FIR filter banks are easily realized from cosine-modulated FIR filter banks by using reciprocal relation and new transformation called cosine-sine modulation in the design of filter banks.

This paper discusses the fixed-point smoothing and filtering problems given lumped covariance function of a scalar signal process observed with additive white Gaussian noise. The recursive Wiener smoother and filter are derived by applying an invariant imbedding method to the Volterra-type integral equation of the second kind in linear least-squares estimation problems. The resultant estimators in Theorem 2 require the information of the crossvariance function of the state variable with the observed value, the system matrix, the observation vector, the variance of the observation noise and the observed value. Here, it is assumed that the signal process is generated by the state-space model. The spectral factorization problem is also considered in Sects. 1 and 2.

We analyze dynamics of a simple hysteresis network (ab. SHN) which has only two parameters. We classify the periodic orbits and clarify the number of attractors and their domain of attraction. The SHN is a piecewise linear system, and therefore we can calculate the trajectory using exact solutions. We clarify the bifurcation sets on which equilibrium attractors bifurcate to the periodic orbits. We also give a sufficient condition for stability of the periodic orbits, and the stability is verified by laboratory experiment. The results of this paper may contribute to the development of an efficient multi functional artificial neural network.

This paper describes the results obtained of a prototype system, VeriProc/1, based on an algorithm we first presented in [13] which can prove the correctness of pipelined processors automatically without pipeline invariant, human interaction, or additional information. No timing relations such as an abstract function or β-relation is required. The only information required is to specify the location of the selectors in the design. The performance is independent of not only data width but also memory size. Detailed analysis of CPU time is presented. Further, don't-care forcing using additional data easily prepared by the user can improve performance.

In this paper, a post-layout optimization technique for power dissipation and timing of cell-based Bipolar ECL LSIs is proposed. An ECL LSI can operate at a frequency of a few GHz but the power dissipation is very high compared to CMOS LSIs, which makes the systems using ECL quite expensive. Therefore it is crucial to develop of CAD techniques that minimize the power dissipation of an ECL LSI without decreasing its performance. To begin with, power and delay models of an ECL gate are presented as functions of its switching current. The power dissipation is a linear function of the switching current and the delay time is its hyperbolic function. These functions are obtained considering the post-layout interconnect capacitance and resistance to make the optimization results accurate enough. Using the delay model, a set of timing constraints specifying the max/min cell delay and the clock skew are extracted. This set of constraints in then given to a nonlinear programming package. The objective functions are clock skew time, the clock cycle time and the power dissipation, which are optimized in this order. With the minimum delay and hold constraints, the problem is not convex so that conventional convex programming approach cannot be used. As a result of the optimization, the switching currents for cells are obtained. These are realized within cells by regulating programmable resistors", which is a special feature of our ECL cell library. Since the above optimization is carried out after the placement and routing of the circuit, it can take accurate delay and power estimation into consideration. Experimental results show more than 40% power reductions for circuits including a real communication system chip, compared to the max power versions. The clock cycle time was maintained or even made faster due to the efficient clock skew optimization.

Pitchmatching algorithms are widely used in layout environments where no grid constraints are imposed. However, realistic layouts include multiple grid constraints which facilitate the applications of automatic routing. Hence, pitchmatching algorithms should be extended to those realistic layouts. This paper formulates a pitchmatching problem with multiple grid constraints. An algorithm for solving this problem is constructed as an extension of conventional pitchmatching algorithms. The computational complexity is also discussed in comparison with a conventional naive algorithm. Finally, examples and application results to realistic layouts are presented.

A algorithm for designing a pattern classifier, which uses MDL criterion and a binary data structure, is proposed. The algorithm gives a partitioning of the range of the multi-dimensional attribute and gives an estimated probability model for this partitioning. The volume of bins in this partitioning is upper bounded by ο((log N/N)^K/(K+2)) almost surely, where N is the length of training sequence and K is the dimension of the attribute. The convergence rates of the code length and the divergence of the estimated model are asymptotically upper bounded by ο((log N/N)^2/(K+2)). The classification error is asymptotically upper bounded by ο((log N/N)^1/(K+2)). Simulation results for 1-dimensional and 2-dimensional attribute cases show that the algorithm is practically efficient.

A system based on application of Fuzzy Cognitive Map (FCM) to perform on-line fault diagnosis is presented. The diagnostic part of the system is composed of two diagnostic schemes. The first one (basic diagnostic algorithm) can be considered as a simple transition of Shiozaki's signed directed graph approach to FCM framework. The second one is an extended version of the basic diagnostic algorithm where an important concept, the temporal associative memories (TAM) recall of FCM, is adopted. In on-line application, self-generated fault FCM model generates predicted pattern sequence through the TAM recall process, which is compared with observed pattern sequence to declare the origin of fault. As the resultant diagnosis scheme takes short computation time, it can be used for on-line fault diagnosis of large and complex processes, and even for incipient fault diagnosis. In practical case, since real observed pattern sequence may be different from predicted one through the TAM recall owing to propagation delay between process variables, the time indexed fault FCM model incorporating delay time is proposed. The utility of the proposed system is illustrated in fault diagnosis of a tank-pipe system.

In this paper, we show that the conventional BCH codes can be better than the AG codes when the number of check symbols is relatively small. More precisely, we consider an AG code on C_ab whose number of check symbols is less than min {g+a, n-g}, where n and g denote the code length and the genus of the curve, respectively. It is shown that there always exists an extended BCH code, (i) which has the same designed distance as the Feng-Rao designed distance of the AG code and the code length and the rate greater than those of the AG code, or (ii) which has the same number of check symbols as that of the AG code, the designed distance not less than that of the AG code and the code length longer than that of the AG code.

In general, a learning machine will behave better as the number of training examples increases. It is important to know how fast and how well the behavior is improved. The average prediction error, the average of the probability that the trained machine mispredicts the output signal, is one of the most popular criteria to see the behavior. However, it is not easy to evaluate the average prediction error even in the simplest case, that is, the linear dichotomy (perceptron) case. When a continuous deterministic dichotomy machine is trained by t examples of input-output pairs produced from a realizable teacher, these examples limits the region of the parameter space which includes the true parameter. Any parameter in the region can explain the input-output behaviors of the examples. Such a region, celled the admissible region, forms in general a (curved) polyhedron in the parameter space, and it becomes smaller and smaller as the number of examples increases. The present paper studies the shape and volume of the admissible region. We use the stochastic geometrical approach to this problem. We have studied the stochastic geometrical features of the admissible region using the fact that it is dual to the convex hull the examples make in the example space. Since the admissible region is related to the average prediction error of the linear dichotomy, we derived the new upper and lower bounds of the average prediction error.

This paper describes a new and realisable speech enhancement structure which simulates the cocktail party effect with a modified iterative Wiener filter and a multi-layer perceptron neural network. The key idea is to use the neural network as a speaker recognition system to govern the iterative Wiener filter. The neural network is a modified perceptron with a hidden layer using feature date extracted from LPC cepstral analysis. The proposed technique has been successfully used for speech enhancement when the interference is competing speech or broad band noise.