In this paper we describe a method for the automated design of analog circuits. The method simultaneously sizes the different components (transistors, capacitors, etc.) in a pre-defined circuit topology and places them according to a pre-defined slicing tree. The method is based on formulating the circuit physical and electrical behavior in a special convex form. More specifically, we cast the design problem as a geometric program, a special type of convex optimization problem. Therefore, all design constraints are formulated as posynomial inequality or monomial equality constraints. Very efficient numerical algorithms are then used to solve the resulting geometric program and to create the design that meets the desired specifications. The formulation is hierarchical and modular, allowing easy topology re-use and process porting. The synthesis method is fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point, and infeasible specifications are unambiguously detected. After a brief overview of current analog design automation solutions, we describe our method and provide some design examples for op-amps and analog-to-digital converters.

This work presents a new sigma-delta modulator (SDM) architecture for a wide bandwidth receiver. This architecture contains dual-bandwidth for W-CDMA and GSM system applications. Low-distortion swing-suppressing SDM and interpolative SDM cascaded units are used together. Using the low-distortion swing-suppressing technique, the resolution can be improved even under non-linearity effects. The interpolative SDM extends the signal bandwidth and represses the high-band noise. The SDM used in the W-CDMA and GSM applications was designed and simulated using 0.25-µm 1P5M CMOS technology. The simulated peak SNDR of W-CDMA and GSM are 72/70 dB and 82/84 dB in Low-IF/Zero-IF standards.

In recent years, digital predistortion linearizers have been used in power amplifiers for mobile communications because they are simpler and provide higher power efficiency than conventional feedforward systems. However, in systems that cover a wider frequency band, it is impossible to disregard the frequency characteristics of their various parameters since the degradation that can result causes a decline in output power efficiency which is the most important property of a power amplifier. To date, no detailed studies have been carried out on predistortion compensation systems. Thus, we focused our research on these systems and in this paper we report the simulation and experimental results we obtained for clarifying these effects. In our experiments, we used a W-CDMA power amplifier to determine how much the distortion compensation effect is degraded by the frequency characteristics of analog RF circuits. The results of experiments to determine the relationship between the ACLR (Adjacent Channel Leakage power Ratio) and power efficiency are also reported.

A CMOS voltage-mode divider, which can operate for low supply voltage and low power dissipation, is presented in this paper. The proposed voltage-mode divider can be used to realize a pseudo-exponential function generator. The experimental results of the proposed voltage-mode divider show that, under the supply voltage V_DD=2.5 V, the linearity error is less than 1.18% and the power consumption is only 102 µW. Also the proposed pseudo-exponential function generator exhibits a 15 dB output dynamic range and the linear error is less than1.54%. Both the proposed circuits have been fabricated in a 0.5 µm N-well CMOS 2P2M process. The proposed circuits are expected to be useful in analog signal processing applications.

In this paper, a new full on-chip high efficiency DC-DC voltage up converter with no inductance element is presented with power efficiency more than 74%. A method in the charge pump is described to have a regulated 3.3 V from 1.5 V for output power 4 mW. For medium power class, 100-200 mW, a boost converter is designed with on-chip inductor for 1.5 V to 3.3 V conversion. A buck converter is also designed for 3.3 V to 1 V conversion with power efficiency 72%. Inductor property of bond-wire is employed in the on-chip inductors. Analysis of efficiency relations and simulation results are presented for 0.35 µm CMOS technology.

A switched capacitor DC-DC voltage converter that has an arbitrary conversion ratio of rational number is presented. A given voltage conversion ratio is systematically expanded to construct a switched capacitor circuit that operates with a two-phase switching clock. The conversion ratio is completely free from capacitance values and ratios under the assumption that there is no charge transfer between the two switching phases. This means that the converter cannot supply any power to the load. This restricts the application of the converters to a very limited area such as a voltage reference generator that only provides a reference voltage and no power to a circuit. The conditions for the convergence of the output voltage and the stray capacitor effects are discussed. The output voltage error and required switching frequency are also discussed when the converter is used as a DC voltage supply source that provides power to a load.

An 8-GS/s 4-bit CMOS analog-to-digital converter (ADC) chip was implemented by using a time interleaved flash architecture for very high frequency mixed signal applications with a 0.18-µm single-poly five-metal CMOS process. Eight 1-GS/s flash ADCs were time-interleaved to achieve the 8-GHz sampling rate. Eight uniformly-spaced 1 GHz clocks were generated by using a phase-locked-loop (PLL) with the peak-to-peak and rms jitters of 29.6 ps and 3.78 ps respectively. An input buffer including a preamplifier array (fifteen preamplifiers, four dummy amplifiers and averaging resistors) was shared among eight 1-GS/s flash ADCs to reduce the input capacitance and the mismatches among eight 1-GS/s flash ADCs. The adjacent output nodes of preamplifiers were connected by a resistor (resistor-averaging) to reduce the effects of the input offset voltage and the load mismatches of preamplifiers. A source follower circuit was added at the output node of a preamplifier to drive eight distributed track and hold (DTH) circuits. The Input bandwidth of ADC was measured to be 2.5 GHz. The measured SFDR values at the sampling rate of 8-GS/s were 25 dB and 22 dB for the 1.033 GHz and 2.5 GHz sinusoidal input signals respectively. The power consumption and the active input voltage range were 340 mW and 700 mV peak-to-peak, respectively, at the sampling rate of 8-GS/s and the supply voltage of 1.8 V. The active chip area was 1.32 mm².

This paper describes the operation and the test results of a novel comparator, called a differential voltage (ΔV) comparator, which detects the difference between two input signal voltages. This comparator utilizes variable threshold voltage inverters (VT-INVs) which can change a logic threshold continuously using a variable channel size MOSFETs (VS-MOSs). The circuit configuration is very simple, and has the potential to achieve high integration and low power consumption in mixed signal system LSIs.

A novel multi-phase charge-sharing technique is proposed for the dot-inversion method to reduce AC power consumption of the TFT-LCD column driver without requiring any external capacitor for charge conservation. Simple and easy-to-control circuitry is applied in the proposed method, and the power saving efficiency depends on number of charge phases. Increasing the number of charge phases, the saving power efficiency is also raised. Excluding power dissipation of switches, the power saving efficiency is up to 75% theoretically with infinite phases. For previous work, the maximum power saving efficient is 50% without external capacitor. The HSPICE simulation results including power dissipation of all switches show that the proposed method with seven charge phases (eight-column lines as one group) decreases the power consumption of 23-68% and 10-18%, respectively, compared with original circuit (without any low-power scheme) and previous low-power charge-recycling works.

Temperature dependence of drain current is analyzed in detail in terms of mobility and threshold voltage. From the analyses, it is proved that a point exists that the drain current is fixed without depending on temperature when the MOSFET operates in strong inversion. Applying this characteristic, a CMOS temperature-voltage converter operating in strong inversion with high linearity is proposed. SPICE simulation and experimental results are shown, and the corresponding performances are discussed.

A neural-signal sensing system with multi-input-channels was designed utilizing a new chopper amplifier with direct connected to a multiplexer. The proposed system consists of multiplexers, chopper amplifiers, a multi-mode analog-to-digital converter (ADC), and a wireless transmitter. It enables to measure 50-channel signals at the same time, which are selected out of 100 channels to detect useful information. The test chip including 10-channel-inputs chopper-amplifier and multi-mode ADC, that was designed and fabricated with a mixed signal 0.35-µm CMOS technology. Utilizing the proposed direct chopper input scheme and the shared chopper amplifier, the circuits was designed with a small area of 9.4 mm². High accuracy channel selecting and multiplexing operations were confirmed, and an equivalent input noise of 10-nV/root-Hz was obtained with test chip measurements. Power dissipation of the chopper amplifier and the ADC were 6.0-mW and 2.5-mW at a 3-V supply voltage, respectively.

A Gm-C filter using multiple-output transconductors suitable for reducing the chip area and power consumption is presented. The novel multiple-output transconductor is based on a translinear gain cell with a linearized input stage. Making good use of the linearized input stage, a simple common-mode feedback is also proposed for this multiple-output transconductor. Using the proposed technique, a 5th-order lowpass filter with two transmission zeros was designed and fabricated as a main part of a lowpass channel selection filter for UMTS receivers. A channel of the filter consumes 7 mA from a 2.7 V power supply and the integrated input-referred noise was 21 dBuV with 20 dB pass band gain. The proposed multiple-output technique saves roughly half the number of transconductors compared with the typical active ladder filter design. The proposed multiple-output transconductors achieve linearization and effective reduction while saving linearized input stages. They are suitable for a filter with small power consumption and small area.

This paper describes synthesis of a complex RⁱCR filter with a finite transmission zero except zero frequency. The frequency response of the proposed filter is similar to the conventional elliptic filter. The proposed filter can be composed of fewer elements than the conventional one. A new kernel function is proposed. As an example, a fifth-order RⁱCR filter is designed. We compare the proposed filter with the conventional complex elliptic filter from the viewpoint of the frequency response and the number of the required elements.

This paper describes an efficient method for the macromodel generation of hybrid systems which are composed of electromagnetic systems and lumped RLC circuits. In our method, electromagnetic systems are formulated as finite-difference frequency-domain (FDFD) equations, and RLC circuits are formulated as nodal equations. Therefore, unlike the partial-element equivalent-circuit (PEEC) method, the technique presented here does not need any 3-dimensional capacitance and inductance parameter extractions to model interconnects, LSI packages and printed circuit boards. Also the lumped RLC elements can be easily included in the hybrid system of equations, thus it is convenient to model some passive components, such as bypass capacitors. The model order reduction technique is utilized in order to construct macromodels from hybrid system of equations. The accuracy of the proposed method is substantiated with some numerical examples.

Two new voltage-mode universal biquadratic filters each with three input signals and one output signal are presented. Each proposed universal biquadratic filter is composed of only two CCIIs, two capacitors and two resistors and can realize all the standard filter functions, that is, highpass, bandpass, lowpass, notch and allpass filters (one more active device is needed for the realization of allpass filter). The proposed circuits have good sensitivities performance and have no requirements for component-matching conditions.

As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.

Nearly 1/f processes are known as important stochastic models for scale invariant data analysis in a number of fields. In this paper, two parameter estimation methods of nearly 1/f processes based on wavelets are proposed. The conventional method based on wavelet transform with EM algorithm does not give the reliable parameter estimation value when the data length is short. Moreover, the precise parameter value is not estimated when the spectrum gap exists in 1/f processes. First, in order to improve the accuracy of the estimation when the data length is short, a parameter estimation method based on wavelet transform with complementary sampling is proposed. Next, in order to reduce the effect of spectrum gap, a parameter estimation method based on wavelet packet with EM algorithm is proposed. Simulation results are given to verify the effectiveness of the proposed methods.

This paper examines the properties of the greatest subsolution for linear equations in the max-plus algebra. The greatest subsolution is a relaxed solution of the linear equations, and gives a unified and reasonable solution whether there exists a strict solution or not. Accordingly, it forms part of a key algorithm for deriving a control law in the field of controller design, and some effective controllers based on the greatest subsolution have been proposed. However, there remain several issues to be discussed regarding the properties of the greatest subsolution. Hence, the main focus of this paper is on the following fundamental properties: 1) Formulation as an optimization problem, 2) Uniqueness of the greatest subsolution, 3) Necessary and sufficient condition for the correspondence of the greatest subsolution with the strict solution. These results could provide flexibility of the controller design based on the greatest subsolution, and facilitate the performance evaluation of the controller. Finally, the uniqueness of the strict solution of the linear equations is examined, and it is confirmed through illustrative examples.

We propose binary-quantized and spatio-temporally discretized network models of linear diffusion systems and investigate their filtering effect on single-bit sigma-delta (ΣΔ) modulated signals. The network consists of only one kind of elements that add ΣΔ modulated signals and quantize the sum in the form of single-bit signal. A basic one-dimensional network is constructed first. Then, the network is extended into two dimensions. These networks have characteristics equivalent to those of linear diffusion systems in both time and frequency domains. In addition, network noise caused by the quantization in the elements contains low-level low-frequency components and high-level high-frequency components. Therefore, the proposed networks have possibility to be used as signal propagation and diffusion media of ΣΔ domain filters.

This paper presents a strictly time- and communication-optimal distributed sorting algorithm in a line network. A strictly time-optimal distributed sorting algorithm in a line network has already been designed. However, its communication complexity is not strictly optimal and it seems to be difficult to extend it to other problems, such as that related to multiple elements in a process, and also the dynamic sorting problem where the number of elements each process should have as its solution is not the same as that in the initial state. Therefore, the algorithm in this paper was designed by an alternative approach to make it strictly time- and communication-optimal. Moreover, an extension to the dynamic sorting problem is described.

Marginal reliability importance (MRI) of a component in a system is defined as the rate at which the system reliability changes over changes of the component reliability. MRI helps network designers to construct a reliable network layout. We consider a problem to compute MRI of all components in a network system considering all-terminal reliability in order to rank the components with respect to MRI. The problem is time-consuming since computing network reliability is #P-complete. This paper improves the traditional approach for the problem to proposes an efficient algorithm. The algorithm applies some network transformations, three network reductions and one network decomposition. We have proved lemmas with respect to the relationship between the transformations and MRI, which compute MRI for an original network by using MRI and reliability for transformed networks. Additionally, we have derived a deformed formula to compute MRI, which can also reduce computational task. Numerical experiments revealed that the proposed algorithm reduced computational time considerably compared to the traditional approach.

Non-repudiation is a basic security requirement for electronic business applications to protect against a sender's false denial of having created and sent a message. Typically non-repudiation protocols are constructed based on digital signatures. However, there has been no theoretical treatment of such non-repudiation protocols. In this paper, we provide a formal security definition of non-repudiation protocols and analyze the security of a signature-based protocol. Our security definition and analysis are based on Canetti's framework of universally composable security.

This paper presents an efficient and generic solution in the following scenario: There are n independent people using variety of signature schemes such as DSS, RSA, Schnorr, and so on, and a subset of them attempts to sign a document without being identified which subset they are. This is a generalized scenario of the Ring Signatures by Rivest, Shamir and Tauman, whose original scenario limits the subset to be a single person and the base signature scheme to be RSA/Rabin schemes. Our scheme allows any signature schemes based on sigma-protocols and claw-free permutations. It also offers shorter signatures and less computation compared to known generic construction. The security is argued in the random oracle model as well as previous schemes and shows that our scheme achieves reduction cost linear in the number of hash queries while it is square for previous generic constructions.

In this paper, a new class of bent functions is constructed by combining class M and class C bent functions. Using the construction method of the class D bent functions defined on the binary vector space, new p-ary generalized bent functions are also introduced for odd prime p.

In this paper, using p-ary bent functions defined on vector space over the finite field F_p^k, we generalized the construction method of the families of p-ary bent sequences with balanced and optimal correlation properties introduced by Kumar and Moreno for an odd prime p, called generalized p-ary bent sequences. It turns out that the family of balanced p-ary sequences with optimal correlation property introduced by Moriuchi and Imamura is a special case of the newly constructed generalized p-ary bent sequences.

We present a learning algorithm of the Hopfield neural network for minimizing edge crossings in linear drawings of nonplanar graphs. The proposed algorithm uses the Hopfield neural network to get a local optimal number of edge crossings, and adjusts the balance between terms of the energy function to make the network escape from the local optimal number of edge crossings. The proposed algorithm is tested on a variety of graphs including some "real word" instances of interconnection networks. The proposed learning algorithm is compared with some existing algorithms. The experimental results indicate that the proposed algorithm yields optimal or near-optimal solutions and outperforms the compared algorithms.

In this paper, we consider a problem of global stabilization of a class of nonlinear systems which are approximately feedback linearizable. We propose a control law with the gain-scaling factor and analytically show the robust aspect of approximate feedback linearization in a more general framework.

The matrix inequality condition has been considered as the main condition for the stability of RHC. But it is difficult to apply the matrix inequality condition for guaranteeing the stability of any physical system because of the high gain problem brought about the high value of the final state weighting matrix. Therefore, in this study, a new stability condition for RHC is proposed and it extends the range of the final state weighting matrix guaranteeing the stability of RHC in comparison with the case of the matrix inequality condition. The proposed stability condition is based not only on a final state weighting matrix but also on a horizon size and guarantees the stability for other forms of model predictive control just like the matrix inequality condition.

A mathematical theory is proposed based on the concept of functional analysis, suitable for operation of network systems extraordinarily complicated and diversified on large scales, through connected-block structures. Fundamental conditions for existence and evaluation of system behaviors of such network systems are obtained in a form of fixed point theorem for system of nonlinear mappings.

In 1983, Chaum first introduced the concept of blind signature. In 2003, Hwang, Lee and Lai pointed out that the Chaum scheme cannot meet the untraceability property of the blind signature scheme. This letter will demonstrate that Hwang et al.'s claim is incorrect and the Chaum blind signature scheme still keeps the untraceability property.

A novel geometrically invariant watermarking scheme based on gravity center is presented which treating the geometrically invariant gravity centers of host image and its supplement image as reference points. Thus watermark synchronization is obtained. Simulation results show the effectiveness of our scheme to the geometrical distortion including rotation and/or scaling.

In this letter, we present an adaptive hopping technique for a wireless personal area network (WPAN) system employing a frequency hop spread spectrum (FH/SS). Analytical results based on the closed-form solutions for the aggregate throughput show that the proposed hopping algorithm using two defined hopping criteria is more friendly towards all kinds of interferers and gives an enhanced throughput with a moderate computational complexity.